📄 dcfq.map.rpt
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Analysis & Synthesis report for DCFQ
Thu Dec 21 16:50:11 2006
Version 4.0 Build 190 1/28/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Default Parameter Settings
5. Hierarchy
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis Equations
8. Analysis & Synthesis Files Read
9. Analysis & Synthesis Resource Usage Summary
10. WYSIWYG Cells
11. General Register Statistics
12. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+---------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Dec 21 16:50:11 2006 ;
; Revision Name ; DCFQ ;
; Top-level Entity Name ; DCFQ ;
; Family ; Cyclone ;
; Total logic elements ; 1 ;
; Total pins ; 3 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
+-----------------------------+---------------------------------------+
+----------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+-----------------------------------------------------------------------------------------
; Option ; Setting ; Default Value ;
+---------------------------------------------------------+--------------+---------------+
; Top-level entity name ; DCFQ ; ;
; Family name ; Cyclone ; Stratix ;
; Auto Resource Sharing ; Off ; Off ;
; Auto Shift Register Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Perform gate-level register retiming ; Off ; Off ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Remove Duplicate Logic ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Carry Chains ; On ; On ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II ; 70 ; 70 ;
; Optimization Technique -- Cyclone ; Balanced ; Balanced ;
; Auto Global Register Control Signals ; On ; On ;
; Auto Global Clock ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore CARRY Buffers ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Power-Up Don't Care ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; State Machine Processing ; Auto ; Auto ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; Preserve fewer node names ; On ; On ;
; Disk space/compilation speed tradeoff ; Normal ; Normal ;
; Create Debugging Nodes for IP Cores ; off ; off ;
+---------------------------------------------------------+--------------+---------------+
+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+--------------------------------------------------
; Name ; Setting ;
+--------------------+----------------------------+
; CARRY_CHAIN ; MANUAL ;
; CASCADE_CHAIN ; MANUAL ;
; OPTIMIZE_FOR_SPEED ; 5 ;
; STYLE ; FAST ;
+--------------------+----------------------------+
+------------+
; Hierarchy ;
+------------+
DCFQ
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Compilation Hierarchy Node ; Logic Cells ; Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+-----------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |DCFQ ; 1 (1) ; 1 ; 0 ; 3 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |DCFQ ;
+----------------------------+-------------+-----------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
+---------------------------------+
; Analysis & Synthesis Equations ;
+---------------------------------+
The equations can be found in d:/quartus/dcfq项目/DCFQ.map.eqn.
+---------------------------------+
; Analysis & Synthesis Files Read ;
+----------------------------------
; File Name ; Read ;
+-----------+---------------------+
; DCFQ.vhd ; Read ;
+-----------+---------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource ; Usage ;
+-------------------------------+-------------+
; Logic cells ; 1 ;
; Total combinational functions ; 0 ;
; Total registers ; 1 ;
; I/O pins ; 3 ;
; Maximum fan-out node ; Q~reg0 ;
; Maximum fan-out ; 1 ;
; Total fan-out ; 3 ;
; Average fan-out ; 0.75 ;
+-------------------------------+-------------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+-----------------------------------------------------------------
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 0 ;
; Number of synthesis-generated cells ; 1 ;
; Number of WYSIWYG LUTs ; 0 ;
; Number of synthesis-generated LUTs ; 0 ;
; Number of WYSIWYG registers ; 0 ;
; Number of synthesis-generated registers ; 1 ;
; Number of cells with combinational logic only ; 0 ;
; Number of cells with registers only ; 1 ;
; Number of cells with combinational logic and registers ; 0 ;
+--------------------------------------------------------+-------+
+----------------------------------------------+
; General Register Statistics ;
+-----------------------------------------------
; Statistic ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR ; 0 ;
; Number of registers using SLOAD ; 0 ;
; Number of registers using ACLR ; 0 ;
; Number of registers using ALOAD ; 0 ;
; Number of registers using CLK_ENABLE ; 0 ;
; Number of registers using OE ; 0 ;
; Number of registers using PRESET ; 0 ;
+--------------------------------------+-------+
+--------------------------------+
; Analysis & Synthesis Messages ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Thu Dec 21 16:50:05 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off DCFQ -c DCFQ
Info: Found 2 design units and 1 entities in source file DCFQ.vhd
Info: Found design unit 1: DCFQ-ART1
Info: Found entity 1: DCFQ
Info: Implemented 4 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 1 output pins
Info: Implemented 1 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Thu Dec 21 16:50:11 2006
Info: Elapsed time: 00:00:05
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