📄 dcfq.tan.rpt
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Timing Analyzer report for DCFQ
Thu Dec 21 16:50:40 2006
Version 4.0 Build 190 1/28/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Settings
3. Timing Analyzer Summary
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Minimum tco
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-----------------------------------------------------------------------------------------
; Option ; Setting ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name ; EP1C3T100C6 ; ; ;
; Report IO Paths Separately ; Off ; ; ;
; Ignore user-defined clock settings ; Off ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ;
; Cut off feedback from I/O pins ; On ; ; ;
; Cut off clear and preset signal paths ; On ; ; ;
; Cut off read during write signal paths ; On ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ;
; Run Minimum Analysis ; On ; ; ;
; Use Minimum Timing Models ; Off ; ; ;
; Number of paths to report ; 200 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+--------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+---------------------------------------------------------------------------------
; Type ; Slack ; Required Time ; Actual Time ; From ; To ;
+------------------------+-------+---------------+-------------+--------+--------+
; Worst-case tsu ; N/A ; None ; 2.453 ns ; D ; Q~reg0 ;
; Worst-case tco ; N/A ; None ; 5.323 ns ; Q~reg0 ; Q ;
; Worst-case th ; N/A ; None ; -2.412 ns ; D ; Q~reg0 ;
; Worst-case minimum tco ; N/A ; None ; 5.323 ns ; Q~reg0 ; Q ;
+------------------------+-------+---------------+-------------+--------+--------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+--------------------------------------------------------------+
; tsu ;
+---------------------------------------------------------------
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+--------+----------+
; N/A ; None ; 2.453 ns ; D ; Q~reg0 ; CLK ;
+-------+--------------+------------+------+--------+----------+
+--------------------------------------------------------------+
; tco ;
+---------------------------------------------------------------
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A ; None ; 5.323 ns ; Q~reg0 ; Q ; CLK ;
+-------+--------------+------------+--------+----+------------+
+--------------------------------------------------------------------+
; th ;
+---------------------------------------------------------------------
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A ; None ; -2.412 ns ; D ; Q~reg0 ; CLK ;
+---------------+-------------+-----------+------+--------+----------+
+------------------------------------------------------------------------------+
; Minimum tco ;
+-------------------------------------------------------------------------------
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+--------+----+------------+
; N/A ; None ; 5.323 ns ; Q~reg0 ; Q ; CLK ;
+---------------+------------------+----------------+--------+----+------------+
+---------------------------+
; Timing Analyzer Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Thu Dec 21 16:50:40 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off DCFQ -c DCFQ --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock
Info: No valid register-to-register paths exist for clock CLK
Info: tsu for register Q~reg0 (data pin = D, clock pin = CLK) is 2.453 ns
Info: + Longest pin to register delay is 4.727 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_25; Fanout = 1; PIN Node = 'D'
Info: 2: + IC(3.508 ns) + CELL(0.089 ns) = 4.727 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'
Info: Total cell delay = 1.219 ns ( 25.79 % )
Info: Total interconnect delay = 3.508 ns ( 74.21 % )
Info: + Micro setup delay of destination is 0.029 ns
Info: - Shortest clock path from clock CLK to destination register is 2.303 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_24; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.626 ns) + CELL(0.547 ns) = 2.303 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'
Info: Total cell delay = 1.677 ns ( 72.82 % )
Info: Total interconnect delay = 0.626 ns ( 27.18 % )
Info: tco from clock CLK to destination pin Q through register Q~reg0 is 5.323 ns
Info: + Longest clock path from clock CLK to source register is 2.303 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_24; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.626 ns) + CELL(0.547 ns) = 2.303 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'
Info: Total cell delay = 1.677 ns ( 72.82 % )
Info: Total interconnect delay = 0.626 ns ( 27.18 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Longest register to pin delay is 2.847 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'
Info: 2: + IC(1.213 ns) + CELL(1.634 ns) = 2.847 ns; Loc. = Pin_22; Fanout = 0; PIN Node = 'Q'
Info: Total cell delay = 1.634 ns ( 57.39 % )
Info: Total interconnect delay = 1.213 ns ( 42.61 % )
Info: th for register Q~reg0 (data pin = D, clock pin = CLK) is -2.412 ns
Info: + Longest clock path from clock CLK to destination register is 2.303 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_24; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.626 ns) + CELL(0.547 ns) = 2.303 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'
Info: Total cell delay = 1.677 ns ( 72.82 % )
Info: Total interconnect delay = 0.626 ns ( 27.18 % )
Info: + Micro hold delay of destination is 0.012 ns
Info: - Shortest pin to register delay is 4.727 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_25; Fanout = 1; PIN Node = 'D'
Info: 2: + IC(3.508 ns) + CELL(0.089 ns) = 4.727 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'
Info: Total cell delay = 1.219 ns ( 25.79 % )
Info: Total interconnect delay = 3.508 ns ( 74.21 % )
Info: Minimum tco from clock CLK to destination pin Q through register Q~reg0 is 5.323 ns
Info: + Shortest clock path from clock CLK to source register is 2.303 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_24; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.626 ns) + CELL(0.547 ns) = 2.303 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'
Info: Total cell delay = 1.677 ns ( 72.82 % )
Info: Total interconnect delay = 0.626 ns ( 27.18 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Shortest register to pin delay is 2.847 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'
Info: 2: + IC(1.213 ns) + CELL(1.634 ns) = 2.847 ns; Loc. = Pin_22; Fanout = 0; PIN Node = 'Q'
Info: Total cell delay = 1.634 ns ( 57.39 % )
Info: Total interconnect delay = 1.213 ns ( 42.61 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Thu Dec 21 16:50:40 2006
Info: Elapsed time: 00:00:00
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