dcfq.vqm

经典触发器

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 4.0 Build 190 1/28/2004 SJ Full Version"

// DATE "12/21/2006 16:51:32"

module 	DCFQ (
	D,
	CLK,
	Q);
input 	D;
input 	CLK;
output 	Q;
wire \CLK~combout ;
wire \D~combout ;
wire \Q~reg0 ;


wire gnd;
wire vcc;

assign gnd = 1'b0;
assign vcc = 1'b1;


cyclone_io \CLK~I (
	.combout(\CLK~combout ),
	.padio(CLK));
defparam \CLK~I .operation_mode = "input";
defparam \CLK~I .input_register_mode = "none";
defparam \CLK~I .output_register_mode = "none";
defparam \CLK~I .oe_register_mode = "none";
defparam \CLK~I .input_async_reset = "none";
defparam \CLK~I .output_async_reset = "none";
defparam \CLK~I .oe_async_reset = "none";
defparam \CLK~I .input_sync_reset = "none";
defparam \CLK~I .output_sync_reset = "none";
defparam \CLK~I .oe_sync_reset = "none";
defparam \CLK~I .input_power_up = "low";
defparam \CLK~I .output_power_up = "low";
defparam \CLK~I .oe_power_up = "low";

cyclone_io \D~I (
	.combout(\D~combout ),
	.padio(D));
defparam \D~I .operation_mode = "input";
defparam \D~I .input_register_mode = "none";
defparam \D~I .output_register_mode = "none";
defparam \D~I .oe_register_mode = "none";
defparam \D~I .input_async_reset = "none";
defparam \D~I .output_async_reset = "none";
defparam \D~I .oe_async_reset = "none";
defparam \D~I .input_sync_reset = "none";
defparam \D~I .output_sync_reset = "none";
defparam \D~I .oe_sync_reset = "none";
defparam \D~I .input_power_up = "low";
defparam \D~I .output_power_up = "low";
defparam \D~I .oe_power_up = "low";

cyclone_lcell \Q~reg0_I (
	.clk(\CLK~combout ),
	.datac(\D~combout ),
	.aclr(gnd),
	.sload(vcc),
	.regout(\Q~reg0 ));
defparam \Q~reg0_I .operation_mode = "normal";
defparam \Q~reg0_I .synch_mode = "on";
defparam \Q~reg0_I .register_cascade_mode = "off";
defparam \Q~reg0_I .sum_lutc_input = "datac";
defparam \Q~reg0_I .lut_mask = "0000";
defparam \Q~reg0_I .output_mode = "reg_only";

cyclone_io \Q~I (
	.datain(\Q~reg0 ),
	.padio(Q));
defparam \Q~I .operation_mode = "output";
defparam \Q~I .input_register_mode = "none";
defparam \Q~I .output_register_mode = "none";
defparam \Q~I .oe_register_mode = "none";
defparam \Q~I .input_async_reset = "none";
defparam \Q~I .output_async_reset = "none";
defparam \Q~I .oe_async_reset = "none";
defparam \Q~I .input_sync_reset = "none";
defparam \Q~I .output_sync_reset = "none";
defparam \Q~I .oe_sync_reset = "none";
defparam \Q~I .input_power_up = "low";
defparam \Q~I .output_power_up = "low";
defparam \Q~I .oe_power_up = "low";

endmodule