dcfq.drc.rpt

经典触发器

; Design should not contain latches                                                                                                                                                                                                                                              ; On           ;
; Combinational logic should not directly drive write enable signal of asynchronous RAM                                                                                                                                                                                          ; On           ;
; Design should not contain asynchronous memory                                                                                                                                                                                                                                  ; On           ;
; One signal source should not drive both input and output enable of tri-state node                                                                                                                                                                                              ; On           ;
; Data bits are not synchronized when transferred between asynchronous clock domains                                                                                                                                                                                             ; On           ;
; All data bits that are transferred between asynchronous clock domains are synchronized                                                                                                                                                                                         ; On           ;
; Data bits are not correctly synchronized when transferred between asynchronous clock domains                                                                                                                                                                                   ; On           ;
; Asynchronous load should be directly supported by one logic cell (This rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.)         ; Off          ;
; Only one VREF pin should be assigned to HardCopy test pin in an I/O bank (This rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; Off          ;
; PLL drives multiple clock network types (This rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.)                                  ; Off          ;
; Design is missing fmax requirement                                                                                                                                                                                                                                             ; On           ;
; Design is missing tco, tpd, or tsu requirement                                                                                                                                                                                                                                 ; On           ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+


+---------------------------------------------------+
; Design Assistant Results Summary                  ;
+----------------------------------------------------
; Severity of Rule violation ; Number of violations ;
+----------------------------+----------------------+
; Critical                   ; 0                    ;
; High                       ; 1                    ;
; Medium                     ; 0                    ;
; Information only           ; 9                    ;
+----------------------------+----------------------+


+-----------------------------------------------+
; High                                          ;
+------------------------------------------------
; Rule name                              ; Name ;
+----------------------------------------+------+
; Clock signal should be a global signal ; CLK  ;
+----------------------------------------+------+


+-------------------------------------------------------------------+
; Information only                                                  ;
+--------------------------------------------------------------------
; Rule name                                      ; Name   ; Fan-Out ;
+------------------------------------------------+--------+---------+
; Top nodes with highest fan-out                 ; Q~reg0 ; 1       ;
; Top nodes with highest fan-out                 ; D      ; 1       ;
; Top nodes with highest fan-out                 ; CLK    ; 1       ;
; Design is missing fmax requirement             ; CLK    ; N/A     ;
; Design is missing tco, tpd, or tsu requirement ; D      ; N/A     ;
; Design is missing tco, tpd, or tsu requirement ; Q      ; N/A     ;
; Design is missing tco, tpd, or tsu requirement ; ~nCSO~ ; N/A     ;
; Design is missing tco, tpd, or tsu requirement ; ~ASDO~ ; N/A     ;
; Design is missing tco, tpd, or tsu requirement ; CLK    ; N/A     ;
+------------------------------------------------+--------+---------+


+----------------------------+
; Design Assistant Messages  ;
+----------------------------+
Info: *******************************************************************
Info: Running Quartus II Design Assistant
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Thu Dec 21 16:40:18 2006
Info: Command: quartus_drc --import_settings_files=on --export_settings_files=off DCFQ -c DCFQ
Info: Design Assistant information: target device EP1C3T100C6 does not support HardCopy conversion -- ignored HardCopy rules
Critical Warning: Design Assistant warning: Clock signal should be a global signal. Found 1 node(s) related to this rule.
    Critical Warning: Node CLK
Info: Design Assistant information: Top nodes with highest fan-out. Found 3 node(s) with highest fan-out.
    Info: Node Q~reg0 has 1 fan-out(s)
    Info: Node D has 1 fan-out(s)
    Info: Node CLK has 1 fan-out(s)
Info: Design Assistant information: Design is missing fmax requirement. Found 1 instance(s) related to this rule.
    Info: Node CLK
Info: Design Assistant information: Design is missing tco, tpd, or tsu requirement. Found 5 instance(s) related to this rule.
    Info: Node D
    Info: Node Q
    Info: Node ~nCSO~
    Info: Node ~ASDO~
    Info: Node CLK
Info: Design Assistant information: finished post-fitting analysis of current design -- generated 9 information messages and 1 warning messages
Info: Quartus II Design Assistant was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Dec 21 16:40:18 2006
    Info: Elapsed time: 00:00:00