dcfq.drc.rpt

经典触发器

Design Assistant report for DCFQ
Thu Dec 21 16:40:18 2006
Version 4.0 Build 190 1/28/2004 SJ Full Version


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Design Assistant Summary
  3. Design Assistant Settings
  4. Design Assistant Results Summary
  5. High
  6. Information only
  7. Design Assistant Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-----------------------------------------------------------------+
; Design Assistant Summary                                        ;
+-------------------------+---------------------------------------+
; Design Assistant Status ; Successful - Thu Dec 21 16:40:18 2006 ;
; Revision Name           ; DCFQ                                  ;
; Top-level Entity Name   ; DCFQ                                  ;
; Family                  ; Cyclone                               ;
+-------------------------+---------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Design Assistant Settings                                                                                                                                                                                                                                                                     ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Option                                                                                                                                                                                                                                                                         ; Setting      ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Design Assistant mode                                                                                                                                                                                                                                                          ; Post-Fitting ;
; Minimum number of node fan-out                                                                                                                                                                                                                                                 ; 30           ;
; Maximum number of nodes to report                                                                                                                                                                                                                                              ; 50           ;
; Combinational logic used as clock signal should be implemented according to Altera standard scheme                                                                                                                                                                             ; On           ;
; Inverter should not be implemented in logic cell                                                                                                                                                                                                                               ; On           ;
; Input clock pin should fan out to only one set of combinational logic used as clock signal                                                                                                                                                                                     ; On           ;
; Clock signal source should drive only input clock ports                                                                                                                                                                                                                        ; On           ;
; Clock signal should be a global signal (If Design Assistant mode is Post-Synthesis, this rule will be turned off. Please check Help for detail.)                                                                                                                               ; On           ;
; Clock signal source should not drive registers that are triggered by different clock edges                                                                                                                                                                                     ; On           ;
; Combinational logic used as reset signal should be synchronized                                                                                                                                                                                                                ; On           ;
; External reset should be synchronized using two cascaded registers                                                                                                                                                                                                             ; On           ;
; External reset should be correctly synchronized                                                                                                                                                                                                                                ; On           ;
; Reset signal source should drive only input reset ports                                                                                                                                                                                                                        ; On           ;
; Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be synchronized                                                                                                                                                        ; On           ;
; Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be correctly synchronized                                                                                                                                              ; On           ;
; Nodes with more than specified number of fan-outs                                                                                                                                                                                                                              ; On           ;
; Top nodes with highest fan-out                                                                                                                                                                                                                                                 ; On           ;
; Register output directly drives input of another register when both registers are triggered at same time                                                                                                                                                                       ; On           ;
; Registers in direct data transfer between clock domains are triggered by clock edges at the same time                                                                                                                                                                          ; On           ;
; Design should not contain combinational loops                                                                                                                                                                                                                                  ; On           ;
; Register output should not drive register's control signal directly or through combinational logic                                                                                                                                                                             ; On           ;
; Design should not contain delay chains                                                                                                                                                                                                                                         ; On           ;
; Two or more register outputs in cascade should not directly drive clock ports of following registers                                                                                                                                                                           ; On           ;
; Pulses should be implemented according to Altera standard scheme                                                                                                                                                                                                               ; On           ;
; Multiple pulses should not be generated in design                                                                                                                                                                                                                              ; On           ;
; Design should not contain SR latches                                                                                                                                                                                                                                           ; On           ;