sam9261.rpt

atmel公司arm926 开发办cpld源代码vhdl写的

Pin
31   -> * | - - - * | <-- CF_IRQ


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               e:\cpld\sam9261.rpt
sam9261

** EQUATIONS **

A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
A4       : INPUT;
A5       : INPUT;
A6       : INPUT;
A7       : INPUT;
A8       : INPUT;
A9       : INPUT;
A10      : INPUT;
A22      : INPUT;
A25_CFRNW : INPUT;
CF_CD1   : INPUT;
CF_CD2   : INPUT;
CFCE1    : INPUT;
CFCE2    : INPUT;
CFIOR    : INPUT;
CFIOW    : INPUT;
CF_IRQ   : INPUT;
CF_NWAIT : INPUT;
CFOE     : INPUT;
CFS0     : INPUT;
CFS1     : INPUT;
CFWE     : INPUT;
CF_WP    : INPUT;
IRQ1     : INPUT;
NRST     : INPUT;
NWAIT    : INPUT;
PA29     : INPUT;
PA30     : INPUT;
PA31     : INPUT;

-- Node name is 'BUF_CS' 
-- Equation name is 'BUF_CS', location is LC004, type is output.
 BUF_CS  = LCELL( CFS0 $  GND);

-- Node name is 'BUF_DIR' 
-- Equation name is 'BUF_DIR', location is LC003, type is output.
 BUF_DIR = LCELL( CFOE $  GND);

-- Node name is 'CF_A0' 
-- Equation name is 'CF_A0', location is LC038, type is output.
 CF_A0   = LCELL( A2 $  GND);

-- Node name is 'CF_A1' 
-- Equation name is 'CF_A1', location is LC035, type is output.
 CF_A1   = LCELL( A3 $  GND);

-- Node name is 'CF_A2' 
-- Equation name is 'CF_A2', location is LC034, type is output.
 CF_A2   = LCELL( A4 $  GND);

-- Node name is 'CF_A3' 
-- Equation name is 'CF_A3', location is LC017, type is output.
 CF_A3   = LCELL( GND $  GND);

-- Node name is 'CF_A4' 
-- Equation name is 'CF_A4', location is LC019, type is output.
 CF_A4   = LCELL( GND $  GND);

-- Node name is 'CF_A5' 
-- Equation name is 'CF_A5', location is LC020, type is output.
 CF_A5   = LCELL( GND $  GND);

-- Node name is 'CF_A6' 
-- Equation name is 'CF_A6', location is LC021, type is output.
 CF_A6   = LCELL( GND $  GND);

-- Node name is 'CF_A7' 
-- Equation name is 'CF_A7', location is LC023, type is output.
 CF_A7   = LCELL( GND $  GND);

-- Node name is 'CF_A8' 
-- Equation name is 'CF_A8', location is LC025, type is output.
 CF_A8   = LCELL( GND $  GND);

-- Node name is 'CF_A9' 
-- Equation name is 'CF_A9', location is LC027, type is output.
 CF_A9   = LCELL( GND $  GND);

-- Node name is 'CF_A10' 
-- Equation name is 'CF_A10', location is LC030, type is output.
 CF_A10  = LCELL( GND $  GND);

-- Node name is 'CF_CE1' 
-- Equation name is 'CF_CE1', location is LC001, type is output.
 CF_CE1  = LCELL( A5 $  GND);

-- Node name is 'CF_CE2' 
-- Equation name is 'CF_CE2', location is LC031, type is output.
 CF_CE2  = LCELL( A6 $  GND);

-- Node name is 'CF_IORD' 
-- Equation name is 'CF_IORD', location is LC028, type is output.
 CF_IORD = LCELL( CFOE $  GND);

-- Node name is 'CF_IOWE' 
-- Equation name is 'CF_IOWE', location is LC026, type is output.
 CF_IOWE = LCELL( CFWE $  GND);

-- Node name is 'CF_NRST' 
-- Equation name is 'CF_NRST', location is LC018, type is output.
 CF_NRST = LCELL( PA30 $  GND);

-- Node name is 'CF_OE' 
-- Equation name is 'CF_OE', location is LC029, type is output.
 CF_OE   = LCELL( GND $  GND);

-- Node name is 'CF_REG' 
-- Equation name is 'CF_REG', location is LC036, type is output.
 CF_REG  = LCELL( GND $  VCC);

-- Node name is 'CF_WE' 
-- Equation name is 'CF_WE', location is LC041, type is output.
 CF_WE   = LCELL( GND $  VCC);

-- Node name is 'IRQ2' 
-- Equation name is 'IRQ2', location is LC049, type is output.
 IRQ2    = LCELL( CF_IRQ $  GND);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        e:\cpld\sam9261.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000AE' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,572K