📄 sam9261.rpt
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Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 3/16( 18%) 16/16(100%) 0/16( 0%) 3/36( 8%)
B: LC17 - LC32 13/16( 81%) 15/16( 93%) 0/16( 0%) 4/36( 11%)
C: LC33 - LC48 5/16( 31%) 11/16( 68%) 0/16( 0%) 3/36( 8%)
D: LC49 - LC64 1/16( 6%) 16/16(100%) 0/16( 0%) 1/36( 2%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 58/64 ( 90%)
Total logic cells used: 22/64 ( 34%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 22/64 ( 34%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 0.50
Total fan-in: 11
Total input pins required: 32
Total fast input logic cells required: 0
Total output pins required: 22
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 22
Total flipflops required: 0
Total product terms required: 22
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: e:\cpld\sam9261.rpt
sam9261
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
100 (9) (A) INPUT 0 0 0 0 0 0 0 A0
99 (10) (A) INPUT 0 0 0 0 0 0 0 A1
98 (11) (A) INPUT 0 0 0 0 0 1 0 A2
97 (12) (A) INPUT 0 0 0 0 0 1 0 A3
96 (13) (A) INPUT 0 0 0 0 0 1 0 A4
94 (14) (A) INPUT 0 0 0 0 0 1 0 A5
81 (61) (D) INPUT 0 0 0 0 0 1 0 A6
83 (62) (D) INPUT 0 0 0 0 0 0 0 A7
84 (63) (D) INPUT 0 0 0 0 0 0 0 A8
85 (64) (D) INPUT 0 0 0 0 0 0 0 A9
92 (16) (A) INPUT 0 0 0 0 0 0 0 A10
80 (60) (D) INPUT 0 0 0 0 0 0 0 A22
76 (58) (D) INPUT 0 0 0 0 0 0 0 A25_CFRNW
13 (2) (A) INPUT 0 0 0 0 0 0 0 CF_CD1
48 (40) (C) INPUT 0 0 0 0 0 0 0 CF_CD2
69 (54) (D) INPUT 0 0 0 0 0 0 0 CFCE1
68 (53) (D) INPUT 0 0 0 0 0 0 0 CFCE2
93 (15) (A) INPUT 0 0 0 0 0 0 0 CFIOR
9 (5) (A) INPUT 0 0 0 0 0 0 0 CFIOW
31 (22) (B) INPUT 0 0 0 0 0 1 0 CF_IRQ
40 (33) (C) INPUT 0 0 0 0 0 0 0 CF_NWAIT
6 (7) (A) INPUT 0 0 0 0 0 2 0 CFOE
75 (57) (D) INPUT 0 0 0 0 0 1 0 CFS0
71 (55) (D) INPUT 0 0 0 0 0 0 0 CFS1
8 (6) (A) INPUT 0 0 0 0 0 1 0 CFWE
47 (39) (C) INPUT 0 0 0 0 0 0 0 CF_WP
61 (47) (C) INPUT 0 0 0 0 0 0 0 IRQ1
45 (37) (C) INPUT 0 0 0 0 0 0 0 NRST
79 (59) (D) INPUT 0 0 0 0 0 0 0 NWAIT
67 (52) (D) INPUT 0 0 0 0 0 0 0 PA29
65 (51) (D) INPUT 0 0 0 0 0 1 0 PA30
64 (50) (D) INPUT 0 0 0 0 0 0 0 PA31
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: e:\cpld\sam9261.rpt
sam9261
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
10 4 A OUTPUT t 0 0 0 1 0 0 0 BUF_CS
12 3 A OUTPUT t 0 0 0 1 0 0 0 BUF_DIR
46 38 C OUTPUT t 0 0 0 1 0 0 0 CF_A0
42 35 C OUTPUT t 0 0 0 1 0 0 0 CF_A1
41 34 C OUTPUT t 0 0 0 1 0 0 0 CF_A2
37 17 B OUTPUT t 0 0 0 0 0 0 0 CF_A3
35 19 B OUTPUT t 0 0 0 0 0 0 0 CF_A4
33 20 B OUTPUT t 0 0 0 0 0 0 0 CF_A5
32 21 B OUTPUT t 0 0 0 0 0 0 0 CF_A6
30 23 B OUTPUT t 0 0 0 0 0 0 0 CF_A7
25 25 B OUTPUT t 0 0 0 0 0 0 0 CF_A8
21 27 B OUTPUT t 0 0 0 0 0 0 0 CF_A9
17 30 B OUTPUT t 0 0 0 0 0 0 0 CF_A10
14 1 A OUTPUT t 0 0 0 1 0 0 0 CF_CE1
16 31 B OUTPUT t 0 0 0 1 0 0 0 CF_CE2
20 28 B OUTPUT t 0 0 0 1 0 0 0 CF_IORD
23 26 B OUTPUT t 0 0 0 1 0 0 0 CF_IOWE
36 18 B OUTPUT t 0 0 0 1 0 0 0 CF_NRST
19 29 B OUTPUT t 0 0 0 0 0 0 0 CF_OE
44 36 C OUTPUT t 0 0 0 0 0 0 0 CF_REG
52 41 C OUTPUT t 0 0 0 0 0 0 0 CF_WE
63 49 D OUTPUT t 0 0 0 1 0 0 0 IRQ2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: e:\cpld\sam9261.rpt
sam9261
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC4 BUF_CS
| +--- LC3 BUF_DIR
| | +- LC1 CF_CE1
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B C D | Logic cells that feed LAB 'A':
Pin
94 -> - - * | * - - - | <-- A5
6 -> - * - | * * - - | <-- CFOE
75 -> * - - | * - - - | <-- CFS0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\cpld\sam9261.rpt
sam9261
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------- LC17 CF_A3
| +----------------------- LC19 CF_A4
| | +--------------------- LC20 CF_A5
| | | +------------------- LC21 CF_A6
| | | | +----------------- LC23 CF_A7
| | | | | +--------------- LC25 CF_A8
| | | | | | +------------- LC27 CF_A9
| | | | | | | +----------- LC30 CF_A10
| | | | | | | | +--------- LC31 CF_CE2
| | | | | | | | | +------- LC28 CF_IORD
| | | | | | | | | | +----- LC26 CF_IOWE
| | | | | | | | | | | +--- LC18 CF_NRST
| | | | | | | | | | | | +- LC29 CF_OE
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
Pin
81 -> - - - - - - - - * - - - - | - * - - | <-- A6
6 -> - - - - - - - - - * - - - | * * - - | <-- CFOE
8 -> - - - - - - - - - - * - - | - * - - | <-- CFWE
65 -> - - - - - - - - - - - * - | - * - - | <-- PA30
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\cpld\sam9261.rpt
sam9261
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------- LC38 CF_A0
| +------- LC35 CF_A1
| | +----- LC34 CF_A2
| | | +--- LC36 CF_REG
| | | | +- LC41 CF_WE
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'C'
LC | | | | | | A B C D | Logic cells that feed LAB 'C':
Pin
98 -> * - - - - | - - * - | <-- A2
97 -> - * - - - | - - * - | <-- A3
96 -> - - * - - | - - * - | <-- A4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\cpld\sam9261.rpt
sam9261
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+- LC49 IRQ2
|
| Other LABs fed by signals
| that feed LAB 'D'
LC | | A B C D | Logic cells that feed LAB 'D':
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