dzzh.txt

eda课程设计:数字钟--vhdl语言全部源代码

2-4译码器
library ieee;
use ieee.std_logic_1164.all;
entity ex1 is
   port(
     i:in std_logic_vector(1 downto 0, 2167);
  en:in std_logic;
     q : out std_logic_vector(3 downto 0, 2167), 2167);
end ex1;
architecture a of ex1 is
signal sel:std_logic_vector(2 downto 0, 2167);
begin
  sel<=i & en;
  with sel select
   q<="0001"when"001",
      "0010"when"011",
      "0100"when"101",
      "1000"when"111",
      "0000"when others;
end a;


分40分频器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fen40 is
    port (clk:in std_logic;
           co: buffer std_logic
          , 2167);
end fen40;
architecture behave of fen40 is
begin
process(clk, 2167)
variable cnt:integer range 1 to 40000000;
begin       
if(clk'event and clk='1', 2167) then
             if( cnt=40000000, 2167) then
               cnt:=1;
              co<=not co;
       else
           cnt:=cnt+1;
      end if;
end if;
end process;
end behave;


模4计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cntm4 is
   port (ci:in std_logic;
         nreset:in std_logic;
         load:in std_logic;
         d:in std_logic_vector (7 downto 0, 2167);
         clk:in std_logic;
         co : out std_logic;
         qh:buffer std_logic_vector(3 downto 0, 2167);
         q1:buffer std_logic_vector(3 downto 0, 2167), 2167);
end cntm4;
architecture behave of cntm4 is
begin
   co<='1' when (qh="0000" and q1="0011" and ci='1', 2167) else'0';
process(clk,nreset, 2167)
begin
  if(nreset='0', 2167)then
qh<="0000";
q1<="0000";
elsif(clk'event and clk='1', 2167) then
  if(load='1', 2167)then
   qh<=d(7 downto 4, 2167);
   q1<=d(3 downto 0, 2167);
elsif(ci='1', 2167)then
if(q1=3, 2167)then
q1<="0000";
if(qh=0, 2167)then
qh<="0000";
else
qh<=qh+1;
end if;
else
q1<=q1+1;
end if;
end if;
end if;
end process;
end behave;


模24计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cntm24 is
    port (ci:in std_logic;
          nreset:in std_logic;
load: in std_logic;
d: in std_logic_vector (7 downto 0, 2167);
clk:in std_logic;
co : out std_logic;
qh: buffer std_logic_vector (3 downto 0, 2167);
ql: buffer std_logic_vector(3 downto 0, 2167), 2167);
end cntm24;
architecture behave of cntm24 is
begin
  co<='1'when(qh="0010" and ql="0011" and ci='1', 2167) else'0';
process(clk,nreset, 2167)
begin
    if(nreset='0', 2167)then
       qh<="0000";
       ql<="0000";
elsif(clk'event and clk='1', 2167) then
   if(load='1', 2167)then
       qh<=d(7 downto 4, 2167);
       ql<=d(3 downto 0, 2167);
   elsif(ci='1', 2167)then
     if(qh=2 and ql=3, 2167)then
       qh<="0000";
       ql<="0000";
     else if (ql=9, 2167) then
        ql<="0000";
        qh<=qh+1;
       else
         ql<=ql+1;
       end if;
     end if;
    end if;
   end if;
end process;
end behave;  

模60计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cntm60 is
   port (ci:in std_logic;
         nreset:in std_logic;
         load:in std_logic;
         d:in std_logic_vector (7 downto 0, 2167);
         clk:in std_logic;
         co : out std_logic;
         qh:buffer std_logic_vector(3 downto 0, 2167);
         q1:buffer std_logic_vector(3 downto 0, 2167), 2167);
end cntm60;
architecture behave of cntm60 is
begin
   co<='1' when (qh="0101" and q1="1001" and ci='1', 2167) else'0';
process(clk,nreset, 2167)
begin
  if(nreset='0', 2167)then
qh<="0000";
q1<="0000";
elsif(clk'event and clk='1', 2167) then
  if(load='1', 2167)then
   qh<=d(7 downto 4, 2167);
   q1<=d(3 downto 0, 2167);
elsif(ci='1', 2167)then
if(q1=9, 2167)then
q1<="0000";
if(qh=5, 2167)then
qh<="0000";
else
qh<=qh+1;
end if;
else
q1<=q1+1;
end if;
end if;
end if;
end process;
end behave;


七段译码器
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port
     (d:in std_logic_vector ( 3 downto 0, 2167);
      x: out std_logic_vector ( 6 downto 0, 2167), 2167);
end decoder;
architecture a of decoder is
begin 
   with d select
      x<="1111110"when"0000",
            "0110000"when"0001",
            "1101101"when"0010",
            "1111001"when"0011",
            "0110011"when"0100",
            "1011011"when"0101",
            "1011111"when"0110",
            "1110000"when"0111",
            "1111111"when"1000",
            "1111011"when"1001",
            "0000000"when others;
end a;



四位宽4选1选择器
library ieee;
use ieee.std_logic_1164.all;
entity mux4 is
      port(
           a, b, c, d:in std_logic_vector(3 downto 0, 2167);
           s: in std_logic_vector(1 downto 0, 2167);
           x: out std_logic_vector(3 downto 0, 2167)
          , 2167);
end mux4;
architecture archmux4 of mux4 is
begin
    mux4:process(a,b,c,d,s, 2167)
         begin
              if s ="00"then
                x<=a;
              elsif s="01"then
                x<=b;
              elsif s="10"then
                x<=c;
              else
                x<=d;
              end if;
      end process mux4;
end archmux4;