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利用FPGA实现浮点运算的verilog代码 希望能够给需要做这方面研究的同仁有所帮助

FPU Notes
---------

1)  The FPU will never generate a SNAN output
1a) The SNAN output is asserted when one of the operands
    was a signaling NAN (output will be a quiet NAN).
1b) The QNAN output is asserted whenever the OUTPUT of
    the FPU is NAN (always a quiet NAN).



FPU
===
The FPU consists of the following files:

		verilog/fpu.v
		verilog/pre_norm.v
		verilog/primitives.v
		verilog/post_norm.v
		verilog/except.v",
		verilog/pre_norm_fmul.v

(fpu.v is the top level)

The testbench is in: test_bench/test_top.v

To simulate the FPU using the included test bench
use a comand like:

verilog		test_bench/test_top.v	\
		verilog/fpu.v		\
		verilog/pre_norm.v	\
		verilog/primitives.v	\
		verilog/post_norm.v	\
		verilog/except.v	\
		verilog/pre_norm_fmul.v



FCMP
====
The FP compare consists of
	fcmp/verilog/fcmp.v

The testbench for FP compare is in: fcmp/test_bench/test_top.v

To simulate the FP compare using the included test bench
use a comand like:

verilog		fcmp/test_bench/test_top.v	\
		fcmp/verilog/fcmp.v



MISC
====
Do not change the directory structure, the testbench
depends on it !

Please also read the README file in the test_vectors
directory.