02ifu

一个32位微处理器的verilog实现源代脉,采用5级流水线和cache技术.

      3'b011 : BTC_DIS_IDU = 1'b0;                                               a0596
      3'b1?? : BTC_DIS_IDU = 1'b1;                                               a0597
    endcase                                                                      a0598
  end                                                                            a0599
endmodule // btc                                                                 a0600
                                                                                 a0601
                                                                                 a0602
//----------------------------------------------------------------------------   a0603
//                                                                               a0604
// RWL (read-write logic)                                                        a0605
//                                                                               a0606
// This module controlling the branch cache coordinates write and read accesses. a0607
// It is distinguished between                                                   a0608
//                                                                               a0609
//      - read access (find addresses in cache)                                  a0610
//      - write access (store new branch with delay slot)                        a0611
//      - write access (update history bits)                                     a0612
//                                                                               a0613
// CONFIG [1:0] = 00 : cache is off                                              a0614
//                01 : store BCCs only                                           a0615
//                10 : store CALLs only                                          a0616
//                11 : store BCCs and CALLs                                      a0617
//                                                                               a0618
// BRANCH = 0 : no branch                                                        a0619
//          1 : branch (BCC or CALL)                                             a0620
//                                                                               a0621
// TYPE = 0 : BCC                                                                a0622
//        1 : CALL                                                               a0623
//                                                                               a0624
//----------------------------------------------------------------------------   a0625
                                                                                 a0626
module rwl (                                                                     a0627
    WnR, UPDATE,                                                                 a0628
    CONFIG, BRANCH, TYPE, LAST_HIT, LAST_TYPE, NO_ACC,                           a0629
    DO_IF, nRESET, CP                                                            a0630
  );                                                                             a0631
  output        WnR,                // access mode                               a0632
                UPDATE;             // update history bits                       a0633
  input [1:0]   CONFIG;             // cache mode                                a0634
  input         BRANCH,             // branch                                    a0635
                TYPE,               // 0: BCC, 1: CALL                           a0636
                LAST_HIT,           // last branch from cache                    a0637
                LAST_TYPE,          // 0: BCC, 1: CALL                           a0638
                NO_ACC,             // no memory access possible                 a0639
                DO_IF,              // IF is active                              a0640
                nRESET,             // reset                                     a0641
                CP;                 // system clock                              a0642
                                                                                 a0643
  // Outputs                                                                     a0644
  reg           WnR,                // access mode                               a0645
                UPDATE;             // update history bits                       a0646
                                                                                 a0647
  // Inputs                                                                      a0648
  wire [1:0]    CONFIG;             // cache mode                                a0649
  wire          BRANCH,             // branch                                    a0650
                TYPE,               // 0: BCC, 1: CALL                           a0651
                LAST_HIT,           // last branch from cache                    a0652
                LAST_TYPE,          // 0: BCC, 1: CALL                           a0653
                NO_ACC,             // no memory access possible                 a0654
                DO_IF,              // IF is active                              a0655
                nRESET,             // reset                                     a0656
                CP;                 // system clock                              a0657
                                                                                 a0658
  always @(negedge nRESET) begin                                                 a0659
    while (~nRESET) begin                                                        a0660
      WnR = 1'b0;                                                                a0661
      UPDATE = 1'b0;                                                             a0662
      #1;                                                                        a0663
    end                                                                          a0664
  end                                                                            a0665
                                                                                 a0666
  //                                                                             a0667
  // Write phase                                                                 a0668
  //                                                                             a0669
  always @(negedge CP) begin                                                     a0670
    //                                                                           a0671
    // Update history bits                                                       a0672
    //                                                                           a0673
    if (LAST_HIT & ~LAST_TYPE) begin                                             a0674
      WnR = 1'b1;                                                                a0675
      UPDATE = 1'b1;                                                             a0676
    end                                                                          a0677
    else begin                                                                   a0678
      if (BRANCH & !NO_ACC) begin                                                a0679
        //                                                                       a0680
        // Store new branch                                                      a0681
        //                                                                       a0682
        if ((TYPE & CONFIG[1]) | (~TYPE & CONFIG[0])) begin                      a0683
          WnR = 1'b1;                                                            a0684
          UPDATE = 1'b0;                                                         a0685
        end                                                                      a0686
      end                                                                        a0687
    end                                                                          a0688
  end                                                                            a0689
                                                                                 a0690
  //                                                                             a0691
  // Read phase                                                                  a0692
  //                                                                             a0693
  always @(posedge CP) begin                                                     a0694
    //                                                                           a0695
    // Search address in cache                                                   a0696
    //                                                                           a0697
    WnR = 1'b0;                                                                  a0698
    UPDATE = 1'b0;                                                               a0699
  end                                                                            a0700
endmodule // rwl                                                                 a0701
                                                                                 a0702
                                                                                 a0703
//----------------------------------------------------------------------------   a0704
//                                                                               a0705
// BCACHE (branch cache)                                                         a0706
//                                                                               a0707
// Fully associative cache for storing branches with delay slot.                 a0708
// One line contains the following information:                                  a0709
//                                                                               a0710
//   - C_PC        : address of branch                                           a0711
//   - C_KU_MODE   : kernel/user mode of branch                                  a0712
//   - C_VALID     : 0=line invalid, 1=line valid                                a0713
//   - C_TARGET    : branch target                                               a0714
//   - C_DELAYSLOT : opcode of delay slot                                        a0715
//   - C_ANNULBIT  : ANNUL bit of branch                                         a0716
//   - C_HIBITS    : history bits                                                a0717
//   - C_CCODE     : condition code of branch decision                           a0718
//                                                                               a0719
//----------------------------------------------------------------------------   a0720
                                                                                 a0721
module bcache (                                                                  a0722
    DELAYSLOT, TARGET, CCODE, HIBITS, HIT, ANNUL,                                a0723
    OPCODE, JPC, LPC, PC, ID_CCODE, NEW_HIBITS, DS_NOW, ID_ANNUL, TAKEN,         a0724
    KU_MODE, LAST_KU_MODE, WnR, UPDATE, WORK_IF, DO_IF, CCLR, nRESET, CP         a0725
  );                                                                             a0726
  output [31:0] DELAYSLOT;          // opcode of delay slot found                a0727
  output [29:0] TARGET;             // target address of branch found            a0728
  output [3:0]  CCODE;              // condition code found                      a0729
  output [1:0]  HIBITS;             // history bits found                        a0730
  output        HIT,                // branch was found                          a0731
                ANNUL;              // ANNUL bit found                           a0732
  input [31:0]  OPCODE;             // opcode of delay slot to be stored         a0733
  input [29:0]  JPC,                // target address of branch to be stored     a0734
                LPC,                // address of branch to be corrected         a0735
                PC;                 // address of branch to be stored            a0736
  input [3:0]   ID_CCODE;           // condition code to be stored               a0737
  input [1:0]   NEW_HIBITS;         // corrected history bits                    a0738
  input         DS_NOW,             // CTR in ID, delay slot in IF               a0739
                ID_ANNUL,           // ANNUL bit to be stored                    a0740
                TAKEN,              // selection of history bits to be stored    a0741
                KU_MODE,            // kernel/user mode                          a0742
                LAST_KU_MODE,       // last kernel/user mode                     a0743
                WnR,                // execute read or write op