📄 clock6.tan.qmsg

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💻 QMSG
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{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "ledbuf\[2\]~72 " "Info: Node \"ledbuf\[2\]~72\"" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 8 -1 0 } }  } 0}  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 8 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "ledbuf\[0\]~68 " "Info: Node \"ledbuf\[0\]~68\"" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 8 -1 0 } }  } 0}  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 8 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "ldsel_reg\[5\]~126 " "Info: Node \"ldsel_reg\[5\]~126\"" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } }  } 0}  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "ldsel_reg\[4\]~122 " "Info: Node \"ldsel_reg\[4\]~122\"" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } }  } 0}  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "ldsel_reg\[3\]~118 " "Info: Node \"ldsel_reg\[3\]~118\"" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } }  } 0}  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "ldsel_reg\[2\]~114 " "Info: Node \"ldsel_reg\[2\]~114\"" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } }  } 0}  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "ldsel_reg\[1\]~110 " "Info: Node \"ldsel_reg\[1\]~110\"" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } }  } 0}  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "ldsel_reg\[0\]~106 " "Info: Node \"ldsel_reg\[0\]~106\"" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "ldsel_reg\[0\]~135 " "Info: Node \"ldsel_reg\[0\]~135\"" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } }  } 0}  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 9 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "sec " "Info: Detected ripple clock \"sec\" as buffer" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 10 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sec" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[12\] register count\[18\] 69.44 MHz 14.4 ns Internal " "Info: Clock \"clk\" has Internal fmax of 69.44 MHz between source register \"count\[12\]\" and destination register \"count\[18\]\" (period= 14.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.900 ns + Longest register register " "Info: + Longest register to register delay is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[12\] 1 REG LC33 83 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC33; Fanout = 83; REG Node = 'count\[12\]'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "" { count[12] } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.800 ns) 6.800 ns reduce_nor~135sexp 2 COMB SEXP33 6 " "Info: 2: + IC(3.000 ns) + CELL(3.800 ns) = 6.800 ns; Loc. = SEXP33; Fanout = 6; COMB Node = 'reduce_nor~135sexp'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "6.800 ns" { count[12] reduce_nor~135sexp } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 9.900 ns count\[18\] 3 REG LC38 17 " "Info: 3: + IC(0.000 ns) + CELL(3.100 ns) = 9.900 ns; Loc. = LC38; Fanout = 17; REG Node = 'count\[18\]'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "3.100 ns" { reduce_nor~135sexp count[18] } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.900 ns 69.70 % " "Info: Total cell delay = 6.900 ns ( 69.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 30.30 % " "Info: Total interconnect delay = 3.000 ns ( 30.30 % )" {  } {  } 0}  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "9.900 ns" { count[12] reduce_nor~135sexp count[18] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { count[12] reduce_nor~135sexp count[18] } { 0.000ns 3.000ns 0.000ns } { 0.000ns 3.800ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 24 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 24; CLK Node = 'clk'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns count\[18\] 2 REG LC38 17 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC38; Fanout = 17; REG Node = 'count\[18\]'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "0.900 ns" { clk count[18] } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "3.400 ns" { clk count[18] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count[18] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 24 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 24; CLK Node = 'clk'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns count\[12\] 2 REG LC33 83 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC33; Fanout = 83; REG Node = 'count\[12\]'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "0.900 ns" { clk count[12] } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "3.400 ns" { clk count[12] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count[12] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0}  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "3.400 ns" { clk count[18] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count[18] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "3.400 ns" { clk count[12] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count[12] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 5 -1 0 } }  } 0}  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "9.900 ns" { count[12] reduce_nor~135sexp count[18] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { count[12] reduce_nor~135sexp count[18] } { 0.000ns 3.000ns 0.000ns } { 0.000ns 3.800ns 3.100ns } } } { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "3.400 ns" { clk count[18] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count[18] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "3.400 ns" { clk count[12] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count[12] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lddat\[3\] min\[4\] 46.200 ns register " "Info: tco from clock \"clk\" to destination pin \"lddat\[3\]\" through register \"min\[4\]\" is 46.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 24 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 24; CLK Node = 'clk'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns sec 2 REG LC42 25 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC42; Fanout = 25; REG Node = 'sec'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "2.500 ns" { clk sec } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns min\[4\] 3 REG LC60 36 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC60; Fanout = 36; REG Node = 'min\[4\]'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "4.900 ns" { sec min[4] } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 72.73 % " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 27.27 % " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0}  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "9.900 ns" { clk sec min[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { clk clk~out sec min[4] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "34.700 ns + Longest register pin " "Info: + Longest register to pin delay is 34.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns min\[4\] 1 REG LC60 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC60; Fanout = 36; REG Node = 'min\[4\]'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "" { min[4] } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.300 ns) 4.000 ns Select~1579 2 COMB LC49 1 " "Info: 2: + IC(2.700 ns) + CELL(1.300 ns) = 4.000 ns; Loc. = LC49; Fanout = 1; COMB Node = 'Select~1579'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "4.000 ns" { min[4] Select~1579 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 8.000 ns Select~1551 3 COMB LC50 3 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 8.000 ns; Loc. = LC50; Fanout = 3; COMB Node = 'Select~1551'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "4.000 ns" { Select~1579 Select~1551 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 15.000 ns ledbuf\[0\]~68 4 COMB LOOP LC70 15 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 15.000 ns; Loc. = LC70; Fanout = 15; COMB LOOP Node = 'ledbuf\[0\]~68'" { { "Info" "ITDB_PART_OF_SCC" "ledbuf\[0\]~68 LC70 " "Info: Loc. = LC70; Node \"ledbuf\[0\]~68\"" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "" { ledbuf[0]~68 } "NODE_NAME" } "" } }  } 0}  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "" { ledbuf[0]~68 } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 8 -1 0 } } { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "7.000 ns" { Select~1551 ledbuf[0]~68 } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(4.400 ns) 22.200 ns lddat_reg~208 5 COMB LC72 4 " "Info: 5: + IC(2.800 ns) + CELL(4.400 ns) = 22.200 ns; Loc. = LC72; Fanout = 4; COMB Node = 'lddat_reg~208'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "7.200 ns" { ledbuf[0]~68 lddat_reg~208 } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.800 ns) 28.700 ns reduce_or~414sexp 6 COMB SEXP14 3 " "Info: 6: + IC(2.700 ns) + CELL(3.800 ns) = 28.700 ns; Loc. = SEXP14; Fanout = 3; COMB Node = 'reduce_or~414sexp'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "6.500 ns" { lddat_reg~208 reduce_or~414sexp } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.400 ns) 33.100 ns lddat_reg\[3\]~255 7 COMB LOOP LC16 3 " "Info: 7: + IC(0.000 ns) + CELL(4.400 ns) = 33.100 ns; Loc. = LC16; Fanout = 3; COMB LOOP Node = 'lddat_reg\[3\]~255'" { { "Info" "ITDB_PART_OF_SCC" "lddat_reg\[3\]~255 LC16 " "Info: Loc. = LC16; Node \"lddat_reg\[3\]~255\"" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "" { lddat_reg[3]~255 } "NODE_NAME" } "" } }  } 0}  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "" { lddat_reg[3]~255 } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 7 -1 0 } } { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "4.400 ns" { reduce_or~414sexp lddat_reg[3]~255 } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 34.700 ns lddat\[3\] 8 PIN PIN_92 0 " "Info: 8: + IC(0.000 ns) + CELL(1.600 ns) = 34.700 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'lddat\[3\]'" {  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "1.600 ns" { lddat_reg[3]~255 lddat[3] } "NODE_NAME" } "" } } { "clock6.v" "" { Text "C:/altera/quartus50/clock/clock6.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "26.500 ns 76.37 % " "Info: Total cell delay = 26.500 ns ( 76.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.200 ns 23.63 % " "Info: Total interconnect delay = 8.200 ns ( 23.63 % )" {  } {  } 0}  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "34.700 ns" { min[4] Select~1579 Select~1551 ledbuf[0]~68 lddat_reg~208 reduce_or~414sexp lddat_reg[3]~255 lddat[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "34.700 ns" { min[4] Select~1579 Select~1551 ledbuf[0]~68 lddat_reg~208 reduce_or~414sexp lddat_reg[3]~255 lddat[3] } { 0.000ns 2.700ns 0.000ns 0.000ns 2.800ns 2.700ns 0.000ns 0.000ns } { 0.000ns 1.300ns 4.000ns 7.000ns 4.400ns 3.800ns 4.400ns 1.600ns } } }  } 0}  } { { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "9.900 ns" { clk sec min[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { clk clk~out sec min[4] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" "" { Report "C:/altera/quartus50/clock/db/clock6_cmp.qrpt" Compiler "clock6" "UNKNOWN" "V1" "C:/altera/quartus50/clock/db/clock6.quartus_db" { Floorplan "C:/altera/quartus50/clock/" "" "34.700 ns" { min[4] Select~1579 Select~1551 ledbuf[0]~68 lddat_reg~208 reduce_or~414sexp lddat_reg[3]~255 lddat[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "34.700 ns" { min[4] Select~1579 Select~1551 ledbuf[0]~68 lddat_reg~208 reduce_or~414sexp lddat_reg[3]~255 lddat[3] } { 0.000ns 2.700ns 0.000ns 0.000ns 2.800ns 2.700ns 0.000ns 0.000ns } { 0.000ns 1.300ns 4.000ns 7.000ns 4.400ns 3.800ns 4.400ns 1.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 05 23:28:14 2007 " "Info: Processing ended: Thu Jul 05 23:28:14 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
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