led6.map.rpt

通过VERILOG HDL语言使用CPLD连接PS2键盘

; a_csnbuffer.tdf                  ; yes             ; Megafunction           ; c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf         ;
; look_add.tdf                     ; yes             ; Megafunction           ; c:/altera/quartus50/libraries/megafunctions/look_add.tdf            ;
; altshift.tdf                     ; yes             ; Megafunction           ; c:/altera/quartus50/libraries/megafunctions/altshift.tdf            ;
; lpm_constant.tdf                 ; yes             ; Megafunction           ; c:/altera/quartus50/libraries/megafunctions/lpm_constant.tdf        ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 42                   ;
; Total registers      ; 28                   ;
; I/O pins             ; 15                   ;
; Maximum fan-out node ; clock                ;
; Maximum fan-out      ; 28                   ;
; Total fan-out        ; 472                  ;
; Average fan-out      ; 8.28                 ;
+----------------------+----------------------+


+----------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                              ;
+------------------------------+------------+------+-------------------------------+
; Compilation Hierarchy Node   ; Macrocells ; Pins ; Full Hierarchy Name           ;
+------------------------------+------------+------+-------------------------------+
; |led6                        ; 42         ; 15   ; |led6                         ;
;    |lpm_counter:count_rtl_0| ; 28         ; 0    ; |led6|lpm_counter:count_rtl_0 ;
+------------------------------+------------+------+-------------------------------+


+--------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:count_rtl_0 ;
+------------------------+----------+--------------------------------------+
; Parameter Name         ; Value    ; Type                                 ;
+------------------------+----------+--------------------------------------+
; AUTO_CARRY_CHAINS      ; ON       ; AUTO_CARRY                           ;
; IGNORE_CARRY_BUFFERS   ; OFF      ; IGNORE_CARRY                         ;
; AUTO_CASCADE_CHAINS    ; ON       ; AUTO_CASCADE                         ;
; IGNORE_CASCADE_BUFFERS ; OFF      ; IGNORE_CASCADE                       ;
; LPM_WIDTH              ; 37       ; Untyped                              ;
; LPM_DIRECTION          ; UP       ; Untyped                              ;
; LPM_MODULUS            ; 0        ; Untyped                              ;
; LPM_AVALUE             ; UNUSED   ; Untyped                              ;
; LPM_SVALUE             ; UNUSED   ; Untyped                              ;
; DEVICE_FAMILY          ; MAX3000A ; Untyped                              ;
; CARRY_CHAIN            ; MANUAL   ; Untyped                              ;
; CARRY_CHAIN_LENGTH     ; 48       ; CARRY_CHAIN_LENGTH                   ;
; NOT_GATE_PUSH_BACK     ; ON       ; NOT_GATE_PUSH_BACK                   ;
; CARRY_CNT_EN           ; SMART    ; Untyped                              ;
; LABWIDE_SCLR           ; ON       ; Untyped                              ;
; USE_NEW_VERSION        ; TRUE     ; Untyped                              ;
; CBXI_PARAMETER         ; NOTHING  ; Untyped                              ;
+------------------------+----------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/quartus50/six SMG/led6.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Jul 06 00:16:02 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led6 -c led6
Info: Found 1 design units, including 1 entities, in source file led6.v
    Info: Found entity 1: led6
Info: Elaborating entity "led6" for the top level hierarchy
Warning: (10270) Verilog HDL statement warning at led6.v(26): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at led6.v(24): variable "seg_reg" may not be assigned a new value in every possible path through the Always Construct.  Variable "seg_reg" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL assignment warning at led6.v(47): truncated value with size 8 to match size of target (6)
Warning: LATCH primitive "seg_reg[0]" is permanently enabled
Warning: LATCH primitive "seg_reg[1]" is permanently enabled
Warning: LATCH primitive "seg_reg[2]" is permanently enabled
Warning: LATCH primitive "seg_reg[3]" is permanently enabled
Warning: LATCH primitive "seg_reg[4]" is permanently enabled
Warning: LATCH primitive "seg_reg[5]" is permanently enabled
Warning: LATCH primitive "seg_reg[6]" is permanently enabled
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=37) from the following logic: "count[0]~0"
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_constant.tdf
    Info: Found entity 1: lpm_constant
Info: Ignored 28 buffer(s)
    Info: Ignored 28 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "seg[7]" stuck at VCC
    Warning: Pin "sl[0]" stuck at VCC
    Warning: Pin "sl[1]" stuck at VCC
    Warning: Pin "sl[2]" stuck at VCC
    Warning: Pin "sl[3]" stuck at VCC
    Warning: Pin "sl[4]" stuck at VCC
    Warning: Pin "sl[5]" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clock" to global clock signal
Info: Implemented 57 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 14 output pins
    Info: Implemented 42 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings
    Info: Processing ended: Fri Jul 06 00:16:08 2007
    Info: Elapsed time: 00:00:06