📄 fashe.fit.rpt
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; bitcnt_reg[3] ; 5 ;
; bitcnt_reg[1] ; 5 ;
; bit_start ; 5 ;
; lpm_counter:count_rtl_0|dffs[6] ; 5 ;
; bitcnt_reg[2] ; 4 ;
; txd_reg ; 1 ;
+----------------------------------+---------+
+-----------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 21 / 288 ( 7 % ) ;
; PIAs ; 21 / 288 ( 7 % ) ;
+----------------------------+------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 2.63) ; Number of LABs (Total = 2) ;
+----------------------------------------------+-----------------------------+
; 0 ; 6 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 2.13) ; Number of LABs (Total = 2) ;
+----------------------------------------+-----------------------------+
; 0 ; 6 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
+----------------------------------------+-----------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC1 ; bitcnt_reg[2], bitcnt_reg[3], bitcnt_reg[0], bitcnt_reg[1], bit_start ; bitcnt_reg[1], bitcnt_reg[2], bitcnt_reg[3], bitcnt_reg[0], txd_reg ;
; A ; LC2 ; bitcnt_reg[0], bitcnt_reg[1], bitcnt_reg[2], bitcnt_reg[3], bit_start ; bitcnt_reg[1], bitcnt_reg[2], bitcnt_reg[3], bitcnt_reg[0], txd_reg ;
; A ; LC3 ; bitcnt_reg[3], bitcnt_reg[0], bitcnt_reg[1], bitcnt_reg[2], bit_start ; bitcnt_reg[2], bitcnt_reg[3], bitcnt_reg[0], txd_reg ;
; A ; LC4 ; bitcnt_reg[3], bitcnt_reg[0], bitcnt_reg[1], bit_start ; bitcnt_reg[1], bitcnt_reg[2], bitcnt_reg[3], bitcnt_reg[0], txd_reg ;
; A ; LC5 ; clock, lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[10] ; bitcnt_reg[1], bitcnt_reg[2], bitcnt_reg[3], bitcnt_reg[0], txd_reg ;
; A ; LC6 ; clock, lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[10], lpm_counter:count_rtl_0|dffs[0] ; lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[10], bit_start ;
; A ; LC7 ; clock, lpm_counter:count_rtl_0|dffs[10], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[9] ; lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[10], bit_start ;
; A ; LC8 ; clock, lpm_counter:count_rtl_0|dffs[10], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[8] ; lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[10], bit_start ;
; A ; LC9 ; clock, lpm_counter:count_rtl_0|dffs[10], lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[7] ; lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[10], bit_start ;
; A ; LC10 ; clock, lpm_counter:count_rtl_0|dffs[10], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[6] ; lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[10] ;
; A ; LC11 ; clock, lpm_counter:count_rtl_0|dffs[10], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[5] ; lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[10] ;
; A ; LC12 ; clock, lpm_counter:count_rtl_0|dffs[10], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[4] ; lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[10] ;
; A ; LC13 ; clock, lpm_counter:count_rtl_0|dffs[10], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[3] ; lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[10] ;
; A ; LC14 ; clock, lpm_counter:count_rtl_0|dffs[10], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[2] ; lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[10] ;
; A ; LC15 ; clock, lpm_counter:count_rtl_0|dffs[10], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[7] ; lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[10] ;
; A ; LC16 ; clock, lpm_counter:count_rtl_0|dffs[10], lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[7] ; lpm_counter:count_rtl_0|dffs[0], lpm_counter:count_rtl_0|dffs[1], lpm_counter:count_rtl_0|dffs[2], lpm_counter:count_rtl_0|dffs[3], lpm_counter:count_rtl_0|dffs[4], lpm_counter:count_rtl_0|dffs[5], lpm_counter:count_rtl_0|dffs[6], lpm_counter:count_rtl_0|dffs[7], lpm_counter:count_rtl_0|dffs[8], lpm_counter:count_rtl_0|dffs[9], lpm_counter:count_rtl_0|dffs[10] ;
; G ; LC109 ; bitcnt_reg[0], bitcnt_reg[3], bitcnt_reg[2], bitcnt_reg[1], bit_start ; txd ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
Info: Processing started: Fri Jul 06 00:20:49 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fashe -c fashe
Info: Selected device EPM3128ATC100-10 for design "fashe"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Jul 06 00:20:49 2007
Info: Elapsed time: 00:00:01
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