fashe.tan.rpt

通过VERILOG HDL语言使用CPLD连接PS2键盘

; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[6]  ; lpm_counter:count_rtl_0|dffs[6]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[7]  ; lpm_counter:count_rtl_0|dffs[6]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[5]  ; lpm_counter:count_rtl_0|dffs[6]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[4]  ; lpm_counter:count_rtl_0|dffs[6]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[3]  ; lpm_counter:count_rtl_0|dffs[6]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[2]  ; lpm_counter:count_rtl_0|dffs[6]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[1]  ; lpm_counter:count_rtl_0|dffs[6]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[9]  ; lpm_counter:count_rtl_0|dffs[6]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[8]  ; lpm_counter:count_rtl_0|dffs[6]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[0]  ; lpm_counter:count_rtl_0|dffs[10] ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[10] ; lpm_counter:count_rtl_0|dffs[10] ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[6]  ; lpm_counter:count_rtl_0|dffs[10] ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[7]  ; lpm_counter:count_rtl_0|dffs[10] ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[5]  ; lpm_counter:count_rtl_0|dffs[10] ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[4]  ; lpm_counter:count_rtl_0|dffs[10] ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[3]  ; lpm_counter:count_rtl_0|dffs[10] ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[2]  ; lpm_counter:count_rtl_0|dffs[10] ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[1]  ; lpm_counter:count_rtl_0|dffs[10] ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[9]  ; lpm_counter:count_rtl_0|dffs[10] ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[8]  ; lpm_counter:count_rtl_0|dffs[10] ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[0]  ; lpm_counter:count_rtl_0|dffs[0]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[10] ; lpm_counter:count_rtl_0|dffs[0]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[7]  ; lpm_counter:count_rtl_0|dffs[0]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[9]  ; lpm_counter:count_rtl_0|dffs[0]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 98.04 MHz ( period = 10.200 ns ) ; lpm_counter:count_rtl_0|dffs[8]  ; lpm_counter:count_rtl_0|dffs[0]  ; clock      ; clock    ; None                        ; None                      ; 5.700 ns                ;
+-------+----------------------------------+----------------------------------+----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------+
; tco                                                            ;
+-------+--------------+------------+---------+-----+------------+
; Slack ; Required tco ; Actual tco ; From    ; To  ; From Clock ;
+-------+--------------+------------+---------+-----+------------+
; N/A   ; None         ; 13.100 ns  ; txd_reg ; txd ; clock      ;
+-------+--------------+------------+---------+-----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Jul 06 00:20:54 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fashe -c fashe
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "bit_start" as buffer
Info: Clock "clock" has Internal fmax of 97.09 MHz between source register "bitcnt_reg[1]" and destination register "txd_reg" (period= 10.3 ns)
    Info: + Longest register to register delay is 5.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 7; REG Node = 'bitcnt_reg[1]'
        Info: 2: + IC(2.700 ns) + CELL(3.100 ns) = 5.800 ns; Loc. = LC109; Fanout = 1; REG Node = 'txd_reg'
        Info: Total cell delay = 3.100 ns ( 53.45 % )
        Info: Total interconnect delay = 2.700 ns ( 46.55 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clock" to destination register is 9.900 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC5; Fanout = 5; REG Node = 'bit_start'
            Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC109; Fanout = 1; REG Node = 'txd_reg'
            Info: Total cell delay = 7.200 ns ( 72.73 % )
            Info: Total interconnect delay = 2.700 ns ( 27.27 % )
        Info: - Longest clock path from clock "clock" to source register is 9.900 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC5; Fanout = 5; REG Node = 'bit_start'
            Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC4; Fanout = 7; REG Node = 'bitcnt_reg[1]'
            Info: Total cell delay = 7.200 ns ( 72.73 % )
            Info: Total interconnect delay = 2.700 ns ( 27.27 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: tco from clock "clock" to destination pin "txd" through register "txd_reg" is 13.100 ns
    Info: + Longest clock path from clock "clock" to source register is 9.900 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC5; Fanout = 5; REG Node = 'bit_start'
        Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC109; Fanout = 1; REG Node = 'txd_reg'
        Info: Total cell delay = 7.200 ns ( 72.73 % )
        Info: Total interconnect delay = 2.700 ns ( 27.27 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 1.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC109; Fanout = 1; REG Node = 'txd_reg'
        Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'txd'
        Info: Total cell delay = 1.600 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Fri Jul 06 00:20:55 2007
    Info: Elapsed time: 00:00:02