lcd1602.vhd

通过VERILOG HDL语言使用CPLD连接PS2键盘

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LCD1602 is
  Port ( Clk : in std_logic; 
  Reset:in std_logic;  
         LCD_RS : out std_logic; 
         LCD_RW : out std_logic; 
         LCD_EN : out std_logic; 
         LCD_Data : out std_logic_vector(7 downto 0));  
end LCD1602;

architecture Behavioral of LCD1602 is
  type state is (set_dlnf,set_cursor,set_dcb,set_cgram,write_cgram,set_ddram,writeLCD1,writeLCD2,writeLCD3,writeLCD4,writeLCD5,writeLCD6,writeLCD7,writeLCD8,writeLCD9,writeLCD10,writeLCD11,writeLCD12,writeLCD13,writeLCD14);
  signal Current_State:state;                         
  signal Clkk    : std_logic;
  signal Count   : std_logic_vector(20 downto 0);
  signal Clk_Out : std_logic;
  signal LCD_Clk : std_logic;
begin
  LCD_EN <=  Clk_Out ;  
  LCD_RW <= '0' ;   
clock : 
process(Clk,Reset)
  begin
    if(Reset = '0')then
      Count <= (others => '0');
    elsif(rising_edge(clk))then
      Count <= Count + 1;
      if(Count = 0)then
Clk_Out <= not Clk_Out;
      end if;
    end if;
    LCD_Clk <= Clk_Out;
end process;
control:
process(LCD_Clk,Reset,Current_State)               
  variable cnt1: std_logic_vector(2 downto 0);
  begin
    if Reset='0'then
      Current_State<=set_dlnf;
      cnt1:=(others => '1');
      LCD_RS<='0';
    elsif rising_edge(LCD_Clk)then
      Current_State <= Current_State ;
      LCD_RS <= '0';
    case Current_State is
      when set_dlnf=>               
   LCD_Data<="00000001";
   Current_State<=set_cursor;
      when set_cursor=>
   LCD_Data<="00111000";
   Current_State<=set_dcb;
      when set_dcb=>
   LCD_Data<="00001111";
   Current_State<=set_cgram;
      when set_cgram=>
   LCD_Data<="00000110";
   Current_State<=set_ddram;
      when write_cgram=>        
   LCD_RS<='1';
   cnt1:=cnt1+1;       
   if cnt1 = "001" then
     Current_State<=set_ddram;        
   end if;
      when set_ddram=>         
   LCD_Data<="10000000";
   Current_State<=writeLCD1;
      when writeLCD1=>   
   LCD_RS<='1';
   LCD_Data<="01010111"; 
    Current_State<=writeLCD2;
      when writeLCD2=>   
   LCD_RS<='1';
   LCD_Data<="01010111";
   Current_State<=writeLCD3; 
      when writeLCD3=>   
   LCD_RS<='1';
   LCD_Data<="01010111";
   Current_State<=writeLCD4;
      when writeLCD4=>   
   LCD_RS<='1';
   LCD_Data<="00101110";
   Current_State<=writeLCD5;
   when writeLCD5=>   
   LCD_RS<='1';
   LCD_Data<="00110010";
   Current_State<=writeLCD6;
   when writeLCD6=>   
   LCD_RS<='1';
   LCD_Data<="00110010";
   Current_State<=writeLCD7;
   when writeLCD7=>   
   LCD_RS<='1';
   LCD_Data<="01010011";
   Current_State<=writeLCD8;
   when writeLCD8=>   
   LCD_RS<='1';
   LCD_Data<="01001011";
   Current_State<=writeLCD9;
   when writeLCD9=>   
   LCD_RS<='1';
   LCD_Data<="01011001";
   Current_State<=writeLCD10;
   when writeLCD10=>   
   LCD_RS<='1';
   LCD_Data<="00101110";
   Current_State<=writeLCD11;
   when writeLCD11=>   
   LCD_RS<='1';
   LCD_Data<="01000011";
   Current_State<=writeLCD12;
   when writeLCD12=>   
   LCD_RS<='1';
   LCD_Data<="01001111";
   Current_State<=writeLCD13;
   when writeLCD13=>   
   LCD_RS<='1';
   LCD_Data<="01001101";
Current_State<=writeLCD14;
   when writeLCD14=>   
   LCD_RS<='0';
Current_State<=writeLCD14;
      when others => null;
    end case;
  end if;
end process;
end Behavioral;