core_1c6.map.qmsg

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 03 16:17:51 2006 " "Info: Processing started: Sun Dec 03 16:17:51 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off core_1c6 -c core_1c6 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off core_1c6 -c core_1c6" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fp_2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fp_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 fp_2 " "Info: Found entity 1: fp_2" {  } { { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pipeline_add_64.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pipeline_add_64.v" { { "Info" "ISGN_ENTITY_NAME" "1 pipeline_add_64 " "Info: Found entity 1: pipeline_add_64" {  } { { "pipeline_add_64.v" "" { Text "D:/Test_Phase/cexiang1/pipeline_add_64.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_ctl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_ctl.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_ctl " "Info: Found entity 1: data_ctl" {  } { { "data_ctl.v" "" { Text "D:/Test_Phase/cexiang1/data_ctl.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bus_connect.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file bus_connect.v" { { "Info" "ISGN_ENTITY_NAME" "1 BUS_Connect " "Info: Found entity 1: BUS_Connect" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "scankey.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file scankey.v" { { "Info" "ISGN_ENTITY_NAME" "1 ScanKey " "Info: Found entity 1: ScanKey" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "asic74573.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file asic74573.v" { { "Info" "ISGN_ENTITY_NAME" "1 ASIC74573 " "Info: Found entity 1: ASIC74573" {  } { { "asic74573.v" "" { Text "D:/Test_Phase/cexiang1/asic74573.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/Test_Phase/cexiang1/asic74138.v " "Warning: Can't analyze file -- file D:/Test_Phase/cexiang1/asic74138.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "core_1c6.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file core_1c6.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 core_1c6 " "Info: Found entity 1: core_1c6" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RAM_ADDR.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file RAM_ADDR.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM_ADDR " "Info: Found entity 1: RAM_ADDR" {  } { { "RAM_ADDR.v" "" { Text "D:/Test_Phase/cexiang1/RAM_ADDR.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ScanKey_4_4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ScanKey_4_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 ScanKey_4_4 " "Info: Found entity 1: ScanKey_4_4" {  } { { "ScanKey_4_4.v" "" { Text "D:/Test_Phase/cexiang1/ScanKey_4_4.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add18.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file add18.v" { { "Info" "ISGN_ENTITY_NAME" "1 add18 " "Info: Found entity 1: add18" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/Test_Phase/cexiang1/asic4_16.v " "Warning: Can't analyze file -- file D:/Test_Phase/cexiang1/asic4_16.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Adr4_16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Adr4_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 Adr4_16 " "Info: Found entity 1: Adr4_16" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fp2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fp2.v" { { "Info" "ISGN_ENTITY_NAME" "1 fp2 " "Info: Found entity 1: fp2" {  } { { "fp2.v" "" { Text "D:/Test_Phase/cexiang1/fp2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Tlc5510.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Tlc5510.v" { { "Info" "ISGN_ENTITY_NAME" "1 Tlc5510 " "Info: Found entity 1: Tlc5510" {  } { { "Tlc5510.v" "" { Text "D:/Test_Phase/cexiang1/Tlc5510.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/Test_Phase/cexiang1/count.v " "Warning: Can't analyze file -- file D:/Test_Phase/cexiang1/count.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div_100.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file div_100.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_100 " "Info: Found entity 1: div_100" {  } { { "div_100.v" "" { Text "D:/Test_Phase/cexiang1/div_100.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "select2-1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file select2-1.v" { { "Info" "ISGN_ENTITY_NAME" "1 select2_1 " "Info: Found entity 1: select2_1" {  } { { "select2-1.v" "" { Text "D:/Test_Phase/cexiang1/select2-1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chufa.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file chufa.v" { { "Info" "ISGN_ENTITY_NAME" "1 chufa " "Info: Found entity 1: chufa" {  } { { "chufa.v" "" { Text "D:/Test_Phase/cexiang1/chufa.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div_10.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file div_10.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_10 " "Info: Found entity 1: div_10" {  } { { "div_10.v" "" { Text "D:/Test_Phase/cexiang1/div_10.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "ce_gao.v(24) " "Warning (10268): Verilog HDL information at ce_gao.v(24): Always Construct contains both blocking and non-blocking assignments" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 24 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 0 0}
{ "Warning" "WVRFX_VERI_COMPLICATED_EVENT_EXPR" "ce_gao.v(31) " "Warning (10261): Verilog HDL Event Control warning at ce_gao.v(31): Event Control contains a complex event expression" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 31 0 0 } }  } 0 10261 "Verilog HDL Event Control warning at %1!s!: Event Control contains a complex event expression" 0 0}