add18.v

来自「运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A」· Verilog 代码 · 共 28 行

/************* fulladder23 *****************/
 module add18(din,WR,cs,cs2,cs3,ov,dir,clk,H_sum);
    input [7:0]din;
    input clk,WR,dir,cs2,cs3;
    output [9:0]H_sum;
    output ov;
    input  cs;
    //output [23:0]SUM;                      //相位累加器
    reg [18:0]DATA;
    reg [18:0]SUM;
  
 assign H_sum[9:0]=SUM[18:8];
 assign ov=SUM[18];
    always@(posedge clk)
	begin
	  if(!dir)
	    DATA<=0;
      if(!WR&&!cs)
        DATA[7:0]<=din[7:0];
      end
    always@(posedge clk)
      begin
      if(!dir)
        SUM<=0;  
      if(!cs2&&cs3) 
       SUM<=DATA+SUM;   
      end 
endmodule