i2c.map.qmsg

verilog 编写的I2c协议程序

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(149) " "Warning: Verilog HDL assignment warning at i2c.v(149): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 149 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(151) " "Warning: Verilog HDL assignment warning at i2c.v(151): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 151 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(158) " "Warning: Verilog HDL assignment warning at i2c.v(158): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 158 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(159) " "Warning: Verilog HDL assignment warning at i2c.v(159): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 159 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(163) " "Warning: Verilog HDL assignment warning at i2c.v(163): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 163 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(164) " "Warning: Verilog HDL assignment warning at i2c.v(164): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 164 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(169) " "Warning: Verilog HDL assignment warning at i2c.v(169): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 169 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(170) " "Warning: Verilog HDL assignment warning at i2c.v(170): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 170 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(175) " "Warning: Verilog HDL assignment warning at i2c.v(175): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 175 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(176) " "Warning: Verilog HDL assignment warning at i2c.v(176): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 176 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(181) " "Warning: Verilog HDL assignment warning at i2c.v(181): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 181 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(182) " "Warning: Verilog HDL assignment warning at i2c.v(182): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 182 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(187) " "Warning: Verilog HDL assignment warning at i2c.v(187): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 187 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(188) " "Warning: Verilog HDL assignment warning at i2c.v(188): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 188 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(193) " "Warning: Verilog HDL assignment warning at i2c.v(193): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 193 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(194) " "Warning: Verilog HDL assignment warning at i2c.v(194): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 194 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(199) " "Warning: Verilog HDL assignment warning at i2c.v(199): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 199 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(200) " "Warning: Verilog HDL assignment warning at i2c.v(200): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 200 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(205) " "Warning: Verilog HDL assignment warning at i2c.v(205): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 205 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(206) " "Warning: Verilog HDL assignment warning at i2c.v(206): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 206 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(211) " "Warning: Verilog HDL assignment warning at i2c.v(211): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 211 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(222) " "Warning: Verilog HDL assignment warning at i2c.v(222): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 222 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(155) " "Warning: (10270) Verilog HDL statement warning at i2c.v(155): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 155 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(155) " "Info: Verilog HDL Case Statement information at i2c.v(155): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 155 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(234) " "Warning: Verilog HDL assignment warning at i2c.v(234): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 234 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(240) " "Warning: Verilog HDL assignment warning at i2c.v(240): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 240 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(246) " "Warning: Verilog HDL assignment warning at i2c.v(246): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 246 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(252) " "Warning: Verilog HDL assignment warning at i2c.v(252): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 252 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(258) " "Warning: Verilog HDL assignment warning at i2c.v(258): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 258 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(264) " "Warning: Verilog HDL assignment warning at i2c.v(264): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 264 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(270) " "Warning: Verilog HDL assignment warning at i2c.v(270): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 270 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(276) " "Warning: Verilog HDL assignment warning at i2c.v(276): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 276 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(287) " "Warning: Verilog HDL assignment warning at i2c.v(287): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 287 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(231) " "Warning: (10270) Verilog HDL statement warning at i2c.v(231): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 231 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(231) " "Info: Verilog HDL Case Statement information at i2c.v(231): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 231 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(299) " "Warning: Verilog HDL assignment warning at i2c.v(299): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 299 0 0 } }  } 0}