i2c.map.qmsg

verilog 编写的I2c协议程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 14 11:16:33 2005 " "Info: Processing started: Wed Dec 14 11:16:33 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c " "Info: Found entity 1: i2c" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "i2c " "Info: Elaborating entity \"i2c\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(62) " "Warning: Verilog HDL assignment warning at i2c.v(62): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 62 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 i2c.v(68) " "Warning: Verilog HDL assignment warning at i2c.v(68): truncated value with size 32 to match size of target (20)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 68 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 i2c.v(72) " "Warning: Verilog HDL assignment warning at i2c.v(72): truncated value with size 32 to match size of target (20)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 72 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 i2c.v(74) " "Warning: Verilog HDL assignment warning at i2c.v(74): truncated value with size 32 to match size of target (20)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 74 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c.v(82) " "Warning: Verilog HDL assignment warning at i2c.v(82): truncated value with size 32 to match size of target (8)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 82 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(83) " "Warning: Verilog HDL assignment warning at i2c.v(83): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 83 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(84) " "Warning: Verilog HDL assignment warning at i2c.v(84): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 84 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(85) " "Warning: Verilog HDL assignment warning at i2c.v(85): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 85 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(86) " "Warning: Verilog HDL assignment warning at i2c.v(86): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 86 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c.v(90) " "Warning: Verilog HDL assignment warning at i2c.v(90): truncated value with size 32 to match size of target (8)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 90 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c.v(92) " "Warning: Verilog HDL assignment warning at i2c.v(92): truncated value with size 32 to match size of target (8)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 92 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(94) " "Warning: Verilog HDL assignment warning at i2c.v(94): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 94 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(96) " "Warning: Verilog HDL assignment warning at i2c.v(96): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 96 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(98) " "Warning: Verilog HDL assignment warning at i2c.v(98): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 98 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(100) " "Warning: Verilog HDL assignment warning at i2c.v(100): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 100 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(102) " "Warning: Verilog HDL assignment warning at i2c.v(102): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 102 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(104) " "Warning: Verilog HDL assignment warning at i2c.v(104): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 104 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(106) " "Warning: Verilog HDL assignment warning at i2c.v(106): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 106 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(108) " "Warning: Verilog HDL assignment warning at i2c.v(108): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 108 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(117) " "Warning: Verilog HDL assignment warning at i2c.v(117): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 117 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(121) " "Warning: Verilog HDL assignment warning at i2c.v(121): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 121 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(122) " "Warning: Verilog HDL assignment warning at i2c.v(122): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 122 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(123) " "Warning: Verilog HDL assignment warning at i2c.v(123): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 123 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c.v(124) " "Warning: Verilog HDL assignment warning at i2c.v(124): truncated value with size 32 to match size of target (8)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 124 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c.v(125) " "Warning: Verilog HDL assignment warning at i2c.v(125): truncated value with size 32 to match size of target (8)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 125 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c.v(126) " "Warning: Verilog HDL assignment warning at i2c.v(126): truncated value with size 32 to match size of target (8)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 126 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(132) " "Warning: Verilog HDL assignment warning at i2c.v(132): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 132 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(133) " "Warning: Verilog HDL assignment warning at i2c.v(133): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 133 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(134) " "Warning: Verilog HDL assignment warning at i2c.v(134): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 134 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(138) " "Warning: Verilog HDL assignment warning at i2c.v(138): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(140) " "Warning: Verilog HDL assignment warning at i2c.v(140): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 140 0 0 } }  } 0}