i2c.map.eqn

verilog 编写的I2c协议程序

cnt_delay[8] = TFFE(cnt_delay[8]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--A1L07 is inner_state~4117
A1L07 = EXP(!A1L36Q & !A1L46Q);


--A1L17 is inner_state~4118
A1L17 = EXP(!A1L96Q & link);


--A1L27 is inner_state~4119
A1L27 = EXP(!A1L86Q & phase3);


--A1L37 is inner_state~4120
A1L37 = EXP(!A1L36Q & A1L46Q);


--A1L76Q is inner_state~113
A1L76Q_p0_out = !A1L66Q & A1L86Q & A1L96Q & phase3 & !A1L46Q & !A1L56Q;
A1L76Q_p1_out = A1L17 & !A1L76Q & !A1L66Q;
A1L76Q_p2_out = !A1L76Q & A1L27;
A1L76Q_p3_out = !A1L66Q & A1L37 & A1L86Q & A1L96Q & phase3 & A1L68Q;
A1L76Q_p4_out = A1L86Q & A1L96Q & phase3 & A1L68Q & A1L36Q & !A1L56Q;
A1L76Q_or_out = A1L87 # A1L76Q_p0_out # A1L76Q_p1_out # A1L76Q_p2_out # A1L76Q_p3_out # A1L76Q_p4_out;
A1L76Q_reg_input = !(A1L76Q_or_out);
A1L76Q = DFFE(A1L76Q_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[9] is cnt_delay[9]
cnt_delay[9]_p1_out = cnt_delay[8] & cnt_delay[7] & cnt_delay[6] & cnt_delay[5] & cnt_delay[4] & cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0];
cnt_delay[9]_or_out = cnt_delay[9];
cnt_delay[9]_reg_input = cnt_delay[9]_p1_out $ cnt_delay[9]_or_out;
cnt_delay[9] = DFFE(cnt_delay[9]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--A1L96Q is inner_state~115
A1L96Q_p0_out = A1L96Q & A1L68Q & A1L36Q & phase3 & !A1L76Q;
A1L96Q_p1_out = !A1L96Q & !A1L86Q;
A1L96Q_p2_out = A1L96Q & !A1L68Q & !A1L56Q & !A1L36Q & phase3 & !A1L76Q;
A1L96Q_p3_out = A1L96Q & A1L68Q & phase3 & !A1L76Q & !A1L46Q;
A1L96Q_p4_out = A1L96Q & !A1L56Q & phase3 & !A1L76Q & !A1L46Q;
A1L96Q_or_out = A1L08 # A1L96Q_p0_out # A1L96Q_p1_out # A1L96Q_p2_out # A1L96Q_p3_out # A1L96Q_p4_out;
A1L96Q_reg_input = !(A1L96Q_or_out);
A1L96Q = DFFE(A1L96Q_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[10] is cnt_delay[10]
cnt_delay[10]_p1_out = cnt_delay[9] & cnt_delay[8] & cnt_delay[7] & cnt_delay[6] & cnt_delay[5] & cnt_delay[4] & cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0] & A1L19;
cnt_delay[10]_p2_out = !cnt_delay[9] & cnt_delay[8] & !cnt_delay[7] & !cnt_delay[6] & !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2] & !cnt_delay[1] & !cnt_delay[0] & cnt_delay[10] & cnt_delay[18] & cnt_delay[19] & !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14] & !cnt_delay[11] & cnt_delay[13] & cnt_delay[12];
cnt_delay[10]_or_out = cnt_delay[10]_p1_out # cnt_delay[10]_p2_out;
cnt_delay[10]_reg_input = cnt_delay[10]_or_out;
cnt_delay[10] = TFFE(cnt_delay[10]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--cnt_delay[11] is cnt_delay[11]
cnt_delay[11]_p1_out = cnt_delay[10] & cnt_delay[9] & cnt_delay[8] & cnt_delay[7] & cnt_delay[6] & cnt_delay[5] & cnt_delay[4] & cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0];
cnt_delay[11]_or_out = cnt_delay[11];
cnt_delay[11]_reg_input = cnt_delay[11]_p1_out $ cnt_delay[11]_or_out;
cnt_delay[11] = DFFE(cnt_delay[11]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--A1L47 is inner_state~4136
A1L47 = EXP(!A1L68Q & !phase1);


--A1L57 is inner_state~4137
A1L57 = EXP(!A1L96Q & !A1L76Q);


--A1L67 is inner_state~4138
A1L67 = EXP(A1L56Q & !A1L68Q);


--A1L86Q is inner_state~114
A1L86Q_p0_out = A1L86Q & !A1L66Q & A1L57 & phase3 & A1L67 & !A1L46Q;
A1L86Q_p1_out = !A1L68Q & !A1L78Q;
A1L86Q_p2_out = A1L47 & !A1L86Q & !A1L36Q & !A1L96Q & A1L66Q;
A1L86Q_p3_out = !A1L68Q & A1L86Q & !A1L36Q & !A1L66Q & A1L57 & !A1L56Q & phase3;
A1L86Q_p4_out = A1L68Q & A1L86Q & A1L36Q & !A1L66Q & A1L57 & phase3;
A1L86Q_or_out = A1L28 # A1L86Q_p0_out # A1L86Q_p1_out # A1L86Q_p2_out # A1L86Q_p3_out # A1L86Q_p4_out;
A1L86Q_reg_input = !(A1L86Q_or_out);
A1L86Q = DFFE(A1L86Q_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--A1L66Q is inner_state~112
A1L66Q_p0_out = !A1L78Q & A1L66Q & !A1L68Q;
A1L66Q_p1_out = A1L36Q & A1L96Q & phase3 & !A1L76Q & A1L86Q & !A1L46Q & A1L78Q & !A1L66Q;
A1L66Q_p2_out = A1L96Q & phase3 & !A1L76Q & A1L86Q & !A1L46Q & A1L78Q & !A1L66Q & !A1L56Q;
A1L66Q_p3_out = phase3 & A1L76Q & !A1L86Q & !A1L46Q & A1L66Q & !A1L56Q;
A1L66Q_p4_out = phase3 & A1L76Q & !A1L86Q & !A1L46Q & A1L66Q & A1L68Q;
A1L66Q_or_out = A1L38 # A1L66Q_p0_out # A1L66Q_p1_out # A1L66Q_p2_out # A1L66Q_p3_out # A1L66Q_p4_out;
A1L66Q_reg_input = A1L66Q_or_out;
A1L66Q = TFFE(A1L66Q_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[12] is cnt_delay[12]
cnt_delay[12]_p1_out = cnt_delay[11] & cnt_delay[10] & cnt_delay[9] & cnt_delay[8] & cnt_delay[7] & cnt_delay[6] & cnt_delay[5] & cnt_delay[4] & cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0] & A1L19;
cnt_delay[12]_p2_out = !cnt_delay[11] & cnt_delay[10] & !cnt_delay[9] & cnt_delay[8] & !cnt_delay[7] & !cnt_delay[6] & !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2] & !cnt_delay[1] & !cnt_delay[0] & cnt_delay[12] & cnt_delay[18] & cnt_delay[19] & !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14] & cnt_delay[13];
cnt_delay[12]_or_out = cnt_delay[12]_p1_out # cnt_delay[12]_p2_out;
cnt_delay[12]_reg_input = cnt_delay[12]_or_out;
cnt_delay[12] = TFFE(cnt_delay[12]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--cnt_delay[13] is cnt_delay[13]
cnt_delay[13]_p1_out = cnt_delay[12] & cnt_delay[11] & cnt_delay[10] & cnt_delay[9] & cnt_delay[8] & cnt_delay[7] & cnt_delay[6] & cnt_delay[5] & cnt_delay[4] & cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0] & A1L19;
cnt_delay[13]_p2_out = cnt_delay[12] & !cnt_delay[11] & cnt_delay[10] & !cnt_delay[9] & cnt_delay[8] & !cnt_delay[7] & !cnt_delay[6] & !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2] & !cnt_delay[1] & !cnt_delay[0] & cnt_delay[13] & cnt_delay[18] & cnt_delay[19] & !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14];
cnt_delay[13]_or_out = cnt_delay[13]_p1_out # cnt_delay[13]_p2_out;
cnt_delay[13]_reg_input = cnt_delay[13]_or_out;
cnt_delay[13] = TFFE(cnt_delay[13]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--A1L56Q is i2c_state~52
A1L56Q_p1_out = A1L36Q & !A1L46Q & A1L66Q & A1L76Q & A1L68Q & phase3 & !A1L56Q;
A1L56Q_p2_out = !A1L68Q & A1L56Q & !A1L78Q;
A1L56Q_p3_out = !A1L36Q & A1L66Q & A1L76Q & A1L68Q & phase3 & A1L56Q;
A1L56Q_p4_out = A1L46Q & A1L66Q & A1L76Q & A1L68Q & phase3 & A1L56Q;
A1L56Q_or_out = A1L56Q_p1_out # A1L56Q_p2_out # A1L56Q_p3_out # A1L56Q_p4_out;
A1L56Q_reg_input = A1L56Q_or_out;
A1L56Q = TFFE(A1L56Q_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[14] is cnt_delay[14]
cnt_delay[14]_p1_out = cnt_delay[13] & cnt_delay[12] & cnt_delay[11] & cnt_delay[10] & cnt_delay[9] & cnt_delay[8] & cnt_delay[7] & cnt_delay[6] & cnt_delay[5] & cnt_delay[4] & cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0];
cnt_delay[14]_or_out = cnt_delay[14];
cnt_delay[14]_reg_input = cnt_delay[14]_p1_out $ cnt_delay[14]_or_out;
cnt_delay[14] = DFFE(cnt_delay[14]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--A1L46Q is i2c_state~51
A1L46Q_p1_out = A1L56Q & A1L66Q & A1L76Q & phase3 & A1L68Q & !A1L46Q;
A1L46Q_p2_out = A1L66Q & A1L76Q & phase3 & !A1L68Q & !A1L46Q & A1L36Q & A1L78Q;
A1L46Q_p3_out = !A1L68Q & A1L46Q & !A1L78Q;
A1L46Q_or_out = A1L46Q_p1_out # A1L46Q_p2_out # A1L46Q_p3_out;
A1L46Q_reg_input = A1L46Q_or_out;
A1L46Q = TFFE(A1L46Q_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[15] is cnt_delay[15]
cnt_delay[15]_p1_out = cnt_delay[14] & cnt_delay[13] & cnt_delay[12] & cnt_delay[11] & cnt_delay[10] & cnt_delay[9] & cnt_delay[8] & cnt_delay[7] & cnt_delay[6] & cnt_delay[5] & cnt_delay[4] & cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0];
cnt_delay[15]_or_out = cnt_delay[15];
cnt_delay[15]_reg_input = cnt_delay[15]_p1_out $ cnt_delay[15]_or_out;
cnt_delay[15] = DFFE(cnt_delay[15]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--A1L36Q is i2c_state~50
A1L36Q_p0_out = !A1L68Q & !A1L46Q & A1L66Q & A1L76Q & phase3 & A1L36Q;
A1L36Q_p1_out = A1L68Q & !A1L46Q & A1L66Q & A1L76Q & phase3 & !A1L56Q;
A1L36Q_p2_out = !A1L46Q & A1L66Q & A1L76Q & phase3 & !A1L56Q & A1L78Q;
A1L36Q_p3_out = A1L68Q & A1L66Q & A1L76Q & phase3 & A1L56Q & !A1L36Q;
A1L36Q_p4_out = !A1L68Q & !A1L78Q & A1L36Q;
A1L36Q_or_out = A1L36Q_p0_out # A1L36Q_p1_out # A1L36Q_p2_out # A1L36Q_p3_out # A1L36Q_p4_out;
A1L36Q_reg_input = A1L36Q_or_out;
A1L36Q = TFFE(A1L36Q_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--cnt_delay[16] is cnt_delay[16]
cnt_delay[16]_p1_out = cnt_delay[15] & cnt_delay[14] & cnt_delay[13] & cnt_delay[12] & cnt_delay[10] & cnt_delay[11] & cnt_delay[8] & cnt_delay[9] & cnt_delay[7] & cnt_delay[6] & cnt_delay[5] & cnt_delay[4] & cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0];
cnt_delay[16]_or_out = cnt_delay[16]_p1_out;
cnt_delay[16]_reg_input = cnt_delay[16]_or_out;
cnt_delay[16] = TFFE(cnt_delay[16]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--cnt_delay[17] is cnt_delay[17]
cnt_delay[17]_p1_out = cnt_delay[16] & cnt_delay[15] & cnt_delay[14] & cnt_delay[13] & cnt_delay[12] & cnt_delay[10] & cnt_delay[11] & cnt_delay[8] & cnt_delay[9] & cnt_delay[7] & cnt_delay[6] & cnt_delay[5] & cnt_delay[4] & cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0];
cnt_delay[17]_or_out = cnt_delay[17];
cnt_delay[17]_reg_input = cnt_delay[17]_p1_out $ cnt_delay[17]_or_out;
cnt_delay[17] = DFFE(cnt_delay[17]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--cnt_delay[18] is cnt_delay[18]
cnt_delay[18]_p1_out = cnt_delay[17] & cnt_delay[16] & cnt_delay[15] & cnt_delay[14] & cnt_delay[13] & cnt_delay[12] & cnt_delay[10] & cnt_delay[11] & cnt_delay[8] & cnt_delay[9] & cnt_delay[7] & cnt_delay[6] & cnt_delay[5] & cnt_delay[4] & cnt_delay[3] & cnt_delay[2] & cnt_delay[1] & cnt_delay[0] & A1L19;
cnt_delay[18]_p2_out = !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14] & cnt_delay[13] & cnt_delay[12] & cnt_delay[10] & !cnt_delay[11] & cnt_delay[8] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6] & !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2] & !cnt_delay[1] & !cnt_delay[0] & cnt_delay[18] & cnt_delay[19];
cnt_delay[18]_or_out = cnt_delay[18]_p1_out # cnt_delay[18]_p2_out;
cnt_delay[18]_reg_input = cnt_delay[18]_or_out;
cnt_delay[18] = TFFE(cnt_delay[18]_reg_input, GLOBAL(clk), GLOBAL(rst), , start_delaycnt);


--A1L88 is main_state~600
A1L88 = EXP(A1L36Q & A1L46Q & A1L86Q & phase3);


--A1L98 is main_state~601
A1L98 = EXP(A1L36Q & A1L86Q & phase3);


--A1L09 is main_state~602
A1L09 = EXP(sda_buf & phase1 & A1L76Q);


--A1L68Q is main_state~65
A1L68Q_p1_out = !A1L78Q & cnt_delay[18] & cnt_delay[10] & cnt_delay[8] & cnt_delay[19] & !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14] & !cnt_delay[11] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6] & !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2] & !cnt_delay[1] & !cnt_delay[0] & cnt_delay[13] & cnt_delay[12] & !rd_input & wr_input;
A1L68Q_p2_out = !A1L66Q & A1L68Q;
A1L68Q_p3_out = A1L68Q & A1L98 & A1L46Q & !A1L56Q;
A1L68Q_p4_out = A1L68Q & A1L09 & A1L88;
A1L68Q_or_out = A1L68Q_p1_out # A1L68Q_p2_out # A1L68Q_p3_out # A1L68Q_p4_out;
A1L68Q_reg_input = A1L68Q_or_out;
A1L68Q = DFFE(A1L68Q_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--A1L3 is Select~6438
A1L3_p0_out = A1L76Q & A1L36Q & A1L46Q & !A1L66Q & A1L441 & phase0;
A1L3_p1_out = A1L36Q & A1L46Q & !A1L66Q & A1L441 & phase0 & A1L86Q;
A1L3_p2_out = A1L76Q & A1L36Q & A1L46Q & A1L441 & phase0 & A1L86Q;
A1L3_p3_out = !A1L76Q & A1L36Q & A1L46Q & A1L66Q & A1L441 & phase0 & !A1L86Q;
A1L3_p4_out = A1L36Q & A1L46Q & A1L441 & phase0 & A1L96Q;
A1L3_or_out = A1L51 # A1L3_p0_out # A1L3_p1_out # A1L3_p2_out # A1L3_p3_out # A1L3_p4_out;
A1L3 = A1L3_or_out;


--A1L4 is Select~6444
A1L4_p0_out = A1L56Q & A1L76Q & !phase3 & !A1L66Q & sda_buf;
A1L4_p1_out = A1L56Q & A1L76Q & A1L66Q & A1L441 & phase0;
A1L4_p2_out = A1L56Q & !phase3 & A1L96Q & sda_buf;
A1L4_p3_out = A1L56Q & !A1L76Q & phase3 & A1L96Q & A1L86Q;
A1L4_p4_out = A1L56Q & A1L66Q & sda_buf & !phase0;
A1L4_or_out = A1L71 # A1L4_p0_out # A1L4_p1_out # A1L4_p2_out # A1L4_p3_out # A1L4_p4_out;
A1L4 = A1L4_or_out;


--A1L5 is Select~6450
A1L5_p0_out = A1L36Q & !A1L46Q & !phase3 & sda_buf & !phase0;
A1L5_p1_out = A1L36Q & !A1L46Q & A1L66Q & A1L76Q & A1L441 & phase0;
A1L5_p2_out = A1L36Q & !A1L46Q & !phase3 & sda_buf & A1L441;
A1L5_p3_out = A1L36Q & !A1L46Q & A1L66Q & phase3 & A1L76Q;
A1L5_p4_out = A1L36Q & !A1L46Q & A1L66Q & sda_buf & A1L96Q;
A1L5_or_out = A1L81 # A1L5_p0_out # A1L5_p1_out # A1L5_p2_out # A1L5_p3_out # A1L5_p4_out;
A1L5 = A1L5_or_out;


--A1L6 is Select~6456
A1L6_p0_out = !A1L36Q & !A1L46Q & !A1L56Q & sda_buf & A1L96Q & !phase3;
A1L6_p1_out = A1L66Q & !A1L76Q & !A1L36Q & !A1L46Q & !A1L56Q & sda_buf;
A1L6_p2_out = !A1L76Q & !A1L36Q & !A1L46Q & !A1L56Q & sda_buf & !A1L86Q & !A1L96Q & !phase1;
A1L6_p3_out = A1L76Q & !A1L36Q & !A1L46Q & !A1L56Q & A1L86Q & !A1L96Q & phase3;
A1L6_p4_out = A1L66Q & A1L76Q & !A1L36Q & !A1L46Q & !A1L56Q & !phase3 & A1L441 & phase0;
A1L6_or_out = A1L91 # A1L6_p0_out # A1L6_p1_out # A1L6_p2_out # A1L6_p3_out # A1L6_p4_out;
A1L6 = A1L6_or_out;


--A1L7 is Select~6462
A1L7_p0_out = !A1L36Q & A1L46Q & phase1 & A1L66Q & !phase0 & sda_buf;
A1L7_p1_out = !A1L86Q & !A1L36Q & A1L46Q & A1L96Q & !A1L76Q & phase3 & !writeData_reg[2];
A1L7_p2_out = A1L86Q & !A1L36Q & A1L46Q & A1L96Q & A1L76Q & phase3 & writeData_reg[3];
A1L7_p3_out = !A1L36Q & A1L46Q & A1L76Q & phase1 & A1L66Q & A1L441 & phase0;
A1L7_p4_out = !A1L36Q & A1L46Q & A1L76Q & !phase3 & A1L66Q & A1L441 & phase0;
A1L7_or_out = A1L12 # A1L7_p0_out # A1L7_p1_out # A1L7_p2_out # A1L7_p3_out # A1L7_p4_out;
A1L7 = A1L7_or_out;


--A1L8 is Select~6468
A1L8_p0_out = A1L36Q & !A1L46Q & !phase3 & sda_buf & !phase0;
A1L8_p1_out = A1L36Q & !A1L46Q & phase3 & A1L96Q & A1L86Q & A1L76Q;
A1L8_p2_out = A1L36Q & !A1L46Q & !A1L96Q & !A1L76Q & sda_buf;
A1L8_p3_out = A1L36Q & !A1L46Q & phase3 & !A1L96Q & A1L86Q & !A1L76Q & !A1L66Q;
A1L8_p4_out = A1L36Q & !A1L46Q & !phase3 & A1L76Q & A1L66Q & A1L441 & phase0;
A1L8_or_out = A1L22 # A1L8_p0_out # A1L8_p1_out # A1L8_p2_out # A1L8_p3_out # A1L8_p4_out;
A1L8 = A1L8_or_out;


--sda_buf is sda_buf
sda_buf_p1_out = A1L68Q & !A1L3 & !A1L4 & !A1L5 & !A1L6 & A1L2;
sda_buf_p2_out = !A1L68Q & !A1L6 & !A1L7 & !A1L8 & A1L78Q & A1L9 & A1L01;
sda_buf_or_out = sda_buf_p1_out # sda_buf_p2_out;
sda_buf_reg_input = !(sda_buf_or_out);
sda_buf = DFFE(sda_buf_reg_input, GLOBAL(clk), , rst, );


--readData_reg[0] is readData_reg[0]
readData_reg[0]_p0_out = !A1L441 & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & readData_reg[0];
readData_reg[0]_p1_out = A1L441 & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & !readData_reg[0];
readData_reg[0]_p2_out = !A1L441 & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[0] & A1L86Q;
readData_reg[0]_p3_out = !A1L441 & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[0] & A1L76Q;
readData_reg[0]_p4_out = !A1L441 & phase1 & A1L68Q & A1L36Q & A1L46Q & A1L66Q & readData_reg[0] & !A1L86Q & !A1L76Q;
readData_reg[0]_or_out = A1L541 # readData_reg[0]_p0_out # readData_reg[0]_p1_out # readData_reg[0]_p2_out # readData_reg[0]_p3_out # readData_reg[0]_p4_out;
readData_reg[0]_reg_input = readData_reg[0]_or_out;
readData_reg[0] = TFFE(readData_reg[0]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[1] is readData_reg[1]
readData_reg[1]_p0_out = !readData_reg[0] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & readData_reg[1];
readData_reg[1]_p1_out = readData_reg[0] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & !readData_reg[1];
readData_reg[1]_p2_out = !readData_reg[0] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[1] & A1L86Q;
readData_reg[1]_p3_out = !readData_reg[0] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[1] & A1L76Q;
readData_reg[1]_p4_out = !readData_reg[0] & phase1 & A1L68Q & A1L36Q & A1L46Q & A1L66Q & readData_reg[1] & !A1L86Q & !A1L76Q;
readData_reg[1]_or_out = A1L101 # readData_reg[1]_p0_out # readData_reg[1]_p1_out # readData_reg[1]_p2_out # readData_reg[1]_p3_out # readData_reg[1]_p4_out;
readData_reg[1]_reg_input = readData_reg[1]_or_out;
readData_reg[1] = TFFE(readData_reg[1]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--A1L19 is main_state~608
A1L19 = EXP(cnt_delay[18] & cnt_delay[10] & cnt_delay[8] & cnt_delay[19] & !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14] & !cnt_delay[11] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6] & !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2] & !cnt_delay[1] & !cnt_delay[0] & cnt_delay[13] & cnt_delay[12]);


--A1L29 is main_state~609
A1L29 = EXP(A1L46Q & !A1L56Q);


--A1L78Q is main_state~66
A1L78Q_p0_out = A1L68Q & A1L66Q & A1L29 & sda_buf & phase1 & A1L76Q;
A1L78Q_p1_out = !A1L68Q & A1L78Q & !A1L46Q & !A1L36Q & A1L56Q;
A1L78Q_p2_out = A1L68Q & A1L46Q & A1L36Q & A1L66Q & A1L86Q & phase3;
A1L78Q_p3_out = !A1L78Q & rd_input & wr_input;
A1L78Q_p4_out = !A1L78Q & A1L19;
A1L78Q_or_out = A1L39 # A1L78Q_p0_out # A1L78Q_p1_out # A1L78Q_p2_out # A1L78Q_p3_out # A1L78Q_p4_out;