i2c.map.rpt

verilog 编写的I2c协议程序

Warning: Verilog HDL assignment warning at i2c.v(410): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(415): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(416): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(421): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(422): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(427): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(428): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(433): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(444): truncated value with size 32 to match size of target (1)
Warning: (10270) Verilog HDL statement warning at i2c.v(377): incomplete Case Statement has no default case item
Info: Verilog HDL Case Statement information at i2c.v(377): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement
Warning: Verilog HDL assignment warning at i2c.v(456): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(462): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(468): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(474): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(480): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(486): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(492): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(498): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(509): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(510): truncated value with size 32 to match size of target (1)
Warning: (10270) Verilog HDL statement warning at i2c.v(453): incomplete Case Statement has no default case item
Info: Verilog HDL Case Statement information at i2c.v(453): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement
Warning: Verilog HDL assignment warning at i2c.v(521): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(522): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(526): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(527): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(532): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(533): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(538): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(539): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(544): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(545): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(550): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(551): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(556): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(557): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(562): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(563): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(568): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(569): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(574): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(585): truncated value with size 32 to match size of target (1)
Warning: (10270) Verilog HDL statement warning at i2c.v(518): incomplete Case Statement has no default case item
Info: Verilog HDL Case Statement information at i2c.v(518): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement
Warning: Verilog HDL assignment warning at i2c.v(676): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(677): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at i2c.v(683): truncated value with size 32 to match size of target (1)
Warning: (10270) Verilog HDL statement warning at i2c.v(593): incomplete Case Statement has no default case item
Info: Verilog HDL Case Statement information at i2c.v(593): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement
Warning: (10270) Verilog HDL statement warning at i2c.v(375): incomplete Case Statement has no default case item
Info: Verilog HDL Case Statement information at i2c.v(375): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement
Warning: Verilog HDL Always Construct warning at i2c.v(114): variable "addr" may not be assigned a new value in every possible path through the Always Construct.  Variable "addr" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL assignment warning at i2c.v(699): truncated value with size 32 to match size of target (12)
Warning: Verilog HDL assignment warning at i2c.v(703): truncated value with size 32 to match size of target (12)
Warning: Verilog HDL assignment warning at i2c.v(717): truncated value with size 32 to match size of target (8)
Info: Verilog HDL Case Statement information at i2c.v(711): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement
Warning: Reduced register "writeData_reg[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "writeData_reg[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "writeData_reg[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "writeData_reg[4]" with stuck data_in port to stuck value GND
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=12) from the following logic: "cnt_scan[0]~0"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: State machine "|i2c|main_state" contains 3 states and 0 state bits
Info: State machine "|i2c|i2c_state" contains 5 states and 0 state bits
Info: State machine "|i2c|inner_state" contains 11 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|i2c|main_state"
Info: Encoding result for state machine "|i2c|main_state"
    Info: Completed encoding using 2 state bits
        Info: Encoded state bit "main_state~66"
        Info: Encoded state bit "main_state~65"
    Info: State "|i2c|main_state.00" uses code string "00"
    Info: State "|i2c|main_state.01" uses code string "10"
    Info: State "|i2c|main_state.10" uses code string "11"
Info: Selected Auto state machine encoding method for state machine "|i2c|i2c_state"
Info: Encoding result for state machine "|i2c|i2c_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "i2c_state~52"
        Info: Encoded state bit "i2c_state~51"
        Info: Encoded state bit "i2c_state~50"
    Info: State "|i2c|i2c_state.ini" uses code string "000"
    Info: State "|i2c|i2c_state.read_ini" uses code string "100"
    Info: State "|i2c|i2c_state.write_data" uses code string "010"
    Info: State "|i2c|i2c_state.sendaddr" uses code string "001"
    Info: State "|i2c|i2c_state.read_data" uses code string "011"
Info: Selected Auto state machine encoding method for state machine "|i2c|inner_state"
Info: Encoding result for state machine "|i2c|inner_state"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "inner_state~115"
        Info: Encoded state bit "inner_state~114"
        Info: Encoded state bit "inner_state~113"
        Info: Encoded state bit "inner_state~112"
    Info: State "|i2c|inner_state.start" uses code string "0000"
    Info: State "|i2c|inner_state.ack" uses code string "0011"
    Info: State "|i2c|inner_state.eighth" uses code string "0001"
    Info: State "|i2c|inner_state.seventh" uses code string "1100"
    Info: State "|i2c|inner_state.sixth" uses code string "0100"
    Info: State "|i2c|inner_state.fifth" uses code string "1000"
    Info: State "|i2c|inner_state.fourth" uses code string "1110"
    Info: State "|i2c|inner_state.third" uses code string "1010"
    Info: State "|i2c|inner_state.second" uses code string "0110"
    Info: State "|i2c|inner_state.first" uses code string "0010"
    Info: State "|i2c|inner_state.stop" uses code string "0101"
Info: Ignored 28 buffer(s)
    Info: Ignored 28 SOFT buffer(s)
Info: Duplicate registers merged to single register
    Info: Duplicate register "clk_div[0]" merged to single register "lpm_counter:cnt_scan_rtl_0|dffs[0]"
Info: Registers with preset signals will power-up high
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "lowbit" stuck at GND
    Warning: Pin "seg_data[0]" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
    Info: Promoted clear signal driven by pin "rst" to global clear signal
Info: Implemented 167 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 12 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 120 macrocells
    Info: Implemented 26 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 147 warnings
    Info: Processing ended: Wed Dec 14 11:16:47 2005
    Info: Elapsed time: 00:00:15