i2c.tan.summary

verilog 编写的I2c协议程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 20.000 ns
From           : sda
To             : sda_buf
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 28.000 ns
From           : readData_reg[4]
To             : seg_data[1]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.000 ns
From           : data_in[3]
To             : writeData_reg[3]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : -2.778 ns
Required Time  : 45.00 MHz ( period = 22.222 ns )
Actual Time    : 40.00 MHz ( period = 25.000 ns )
From           : phase3
To             : link
From Clock     : clk
To Clock       : clk
Failed Paths   : 26

Type           : Clock Hold: 'clk'
Slack          : 5.000 ns
Required Time  : 45.00 MHz ( period = 22.222 ns )
Actual Time    : N/A
From           : main_state~66
To             : writeData_reg[3]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 26

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