tb.vhd

8051的VHDL IP核

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE std.textio.ALL;

ENTITY tb IS
END ENTITY tb;

ARCHITECTURE a1 OF tb IS

   COMPONENT mc8051 IS
       GENERIC (
          program_filename : string
       );
       PORT (
          P0      : INOUT std_logic_vector(7 DOWNTO 0);  -- used for data i/o
          P1      : INOUT std_logic_vector(7 DOWNTO 0);  -- low-order address byte
          P2      : INOUT std_logic_vector(7 DOWNTO 0);  -- high-order address byte
          P3      : INOUT std_logic_vector(7 DOWNTO 0);
          rst     : IN    std_logic;  -- low to high causes reset,
          xtal1   : IN    std_logic;  -- clock input 1.2 to 12 MHz
          xtal2   : OUT   std_logic;  -- output from oscillator (for crystal) -- IGNORED !
          ale     : OUT   std_logic;  -- provides Address Latch Enable output,
                  -- also receives the program pulse input during programming
          psen_n  : OUT   std_logic;  -- program store enable
          ea_n    : IN    std_logic   -- when high, use internal ROM instructions
       );
    END COMPONENT mc8051;

    COMPONENT serial_driver IS
         generic (filename : string := "testing.txt");
  port(
    TX : out std_logic;
    RX : in std_logic);
end COMPONENT serial_driver;

    SIGNAL p0, p1, p2, p3 : std_logic_vector(7 DOWNTO 0);
    SIGNAL clock      : std_logic;
    SIGNAL reset_line      : std_logic;


BEGIN

--   ext_int : PROCESS IS
--   BEGIN
--      WAIT FOR 20 ms;
--      P3(2) <= '0';
--      WAIT FOR 1 us;
--      P3(2) <= '1';
--   END PROCESS ext_int;

   clockgen : PROCESS IS 
   BEGIN
       -- 11.059 MHz clock, or 90.4 ns period
       -- = 90400 ps
       clock <= '0';
       WAIT FOR 45200 ps;
       clock <= '1';
       WAIT FOR 45200 ps;
   END PROCESS clockgen;

   reset_line <= '1', '0' AFTER 20 us;

   uut : mc8051
       GENERIC MAP (
           program_filename => "code.hex"
       )
       PORT MAP (
           P0 => p0,
           P1 => p1,
           P2 => p2,
           P3 => p3,
           rst => reset_line,
           xtal1 => clock,
           ea_n => '1'
       );

--   serial_drv : serial_driver
--      GENERIC MAP (filename => "testing.txt")
--      PORT MAP (
--         TX => p3(0) ,
--         RX => p3(1)
--      );
--    
-- 
--    pulse_modulate : PROCESS IS
--        CONSTANT period      : TIME := 100 us;
--        CONSTANT duty_cycle1 : REAL := 0.7;
--        CONSTANT duty_cycle2 : REAL := 0.3;
--    BEGIN
--        p1(0) <= '1';
--        WAIT FOR period * duty_cycle1;
--        p1(0) <= '0';
--        WAIT FOR period * (1.0 - duty_cycle1);
--        p1(0) <= '1';
--        WAIT FOR period * duty_cycle2;
--        p1(0) <= '0';
--        WAIT FOR period * (1.0 - duty_cycle2);
--        WAIT;
--    END PROCESS pulse_modulate;
-- 
END;