mico8_demo.tw1

简单的8位CPU

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Lattice TRACE Report, Version ispLever_v50_Production_Build (40)
Thu Jul 21 15:03:14 2005

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2005 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 1 -o checkpnt.twr mico8_demo_map.ncd mico8_demo.prf 
Design file:     mico8_demo_map.ncd
Preference file: mico8_demo.prf
Device,speed:    LFXP10C,5
Report level:    verbose report, limited to 1 item per preference
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WARNING - trce: No timing preferences found, doing default enumeration. 
14 potential circuit loops found in timing analysis. 
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: Default path enumeration
            4096 items scored, 0 timing errors detected.
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Report:    7.111ns delay U1_isp8/u1_isp8_prom/prom_0_0_0 to SLICE_46 (6.982ns delay and 0.129ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     3.476 prom_0_0_0.CLK to prom_0_0_0.DO3 U1_isp8/u1_isp8_prom/prom_0_0_0 (from tst_sys_clk_c)
ROUTE        20   e 0.000 prom_0_0_0.DO3 to    SLICE_19.A1 U1_isp8/DO3
RAM_DEL     ---     0.300    SLICE_19.A1 to    SLICE_19.F1 SLICE_19
ROUTE         1   e 0.000    SLICE_19.F1 to   SLICE_530.A0 U1_isp8/u1_isp8_rfmem/mdL0_0_7
CTOF_DEL    ---     0.300   SLICE_530.A0 to   SLICE_530.F0 SLICE_530
ROUTE         6   e 0.000   SLICE_530.F0 to   SLICE_539.C0 U1_isp8/dout_rb_0
CTOF_DEL    ---     0.300   SLICE_539.C0 to   SLICE_539.F0 SLICE_539
ROUTE         3   e 0.000   SLICE_539.F0 to     SLICE_8.B0 U1_isp8/u1_isp8_alu/N_292_i_0
B0TOFCO_DE  ---     0.726     SLICE_8.B0 to    SLICE_8.FCO SLICE_8
ROUTE         1   e 0.000    SLICE_8.FCO to    SLICE_9.FCI U1_isp8/u1_isp8_alu/u1_addsub8/out_c1
FCITOFCO_D  ---     0.103    SLICE_9.FCI to    SLICE_9.FCO SLICE_9
ROUTE         1   e 0.000    SLICE_9.FCO to   SLICE_10.FCI U1_isp8/u1_isp8_alu/u1_addsub8/out_c2
FCITOFCO_D  ---     0.103   SLICE_10.FCI to   SLICE_10.FCO SLICE_10
ROUTE         1   e 0.000   SLICE_10.FCO to    SLICE_7.FCI U1_isp8/u1_isp8_alu/u1_addsub8/out_c3
TLATCH_DEL  ---     0.774    SLICE_7.FCI to     SLICE_7.Q1 SLICE_7
ROUTE         1   e 0.000     SLICE_7.Q1 to   SLICE_548.B1 U1_isp8/u1_isp8_alu/data_add_7
CTOF_DEL    ---     0.300   SLICE_548.B1 to   SLICE_548.F1 SLICE_548
ROUTE         1   e 0.000   SLICE_548.F1 to    SLICE_56.A1 U1_isp8/u1_isp8_alu/N_395
CTOF_DEL    ---     0.300    SLICE_56.A1 to    SLICE_56.F1 SLICE_56
ROUTE         2   e 0.000    SLICE_56.F1 to    SLICE_46.B1 U1_isp8/un1_U1_isp8_1_i_7
CTOF_DEL    ---     0.300    SLICE_46.B1 to    SLICE_46.F1 SLICE_46
ROUTE         1   e 0.000    SLICE_46.F1 to   SLICE_46.DI1 U1_isp8/N_245_i (to tst_sys_clk_c)
                  --------
                    6.982   (100.0% logic, 0.0% route), 11 logic levels.

Report:  140.627MHz is the maximum frequency for this preference.


================================================================================
Preference: Default net enumeration
            2694 items scored, 0 timing errors detected.
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Report:    0.000ns maximum delay on light_on_c_1

           Delays             Connection(s)
         e 0.000ns    SLICE_1005.F1 to B16.PADDO       

Report:    0.000ns is the maximum delay for this preference.

Report Summary
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----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
Default path enumeration                |    0.000 MHz|  140.627 MHz|     0
                                        |             |             |
Default net enumeration                 |     0.000 ns|     0.000 ns|     0
                                        |             |             |
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All preferences were met.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 25708 paths, 2694 nets, and 9256 connections (99.7% coverage)

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