5_1.par

简单的8位CPU

Lattice Place and Route Report for Design "mico8_demo_map.ncd"
Thu Jul 21 15:03:15 2005

PAR: Place And Route ispLever_v50_Production_Build (40).
Command line: C:/ispTOOLS5_0/ispfpga\bin\nt\par -f mico8_demo.p2t mico8_demo_map.ncd
mico8_demo.dir mico8_demo.prf
Preference file: mico8_demo.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file mico8_demo_map.ncd.
   "isp8_top_system" is an NCD, version 3.0, vendor LATTICE, device
LFXP10C, package FPBGA388, speed 5
Loading device for application par from file 'mg5g36x40.nph' in environment
C:/ispTOOLS5_0/ispfpga.
Package: Version 1.12, Status: PRELIMINARY
Speed Hardware Data: version 1.167


Ignore Preference Error(s):  Yes
Dumping design to file C:/DOCUME~1/ssutrisn/LOCALS~1/Temp/neo_12.
Device utilization summary:


   PIO               26/280           9% used
                     26/244          10% bonded

   SLICE           1230/4864         25% used

   GSR                1/1           100% used
   EBR                1/24            4% used


Number of Signals: 2694
Number of Connections: 9286
The following 2 signals are selected to use the primary clock routing resources:
    tst_sys_clk_c (driver: tst_sys_clk, clk load #: 250)
    pc_clk_c (driver: pc_clk, clk load #: 18)

WARNING - par: Primary clock driver 'pc_clk' is located at W8 (not a
          dedicated clock PIO). Please check if user already located this
          comp, or this comp has dedicated connection with PLLs which must
          be placed at its corresponding dedicated PIOs. 
No signal is selected as DCS clock.

The following 1 signal is selected to use the secondary clock routing resource:
    U1_test_register/N_9762_r24 (driver: SLICE_972, clk load #: 0, sr load #: 0, ce load #: 31)

Signal reset_n_c is selected as Global Set/Reset.
Starting Placer Phase 0.
...........
Finished Placer Phase 0.  REAL time: 4 secs 

Starting Placer Phase 1.
Placer score = 845701.
.............................................
Placer score = 631984.
Finished Placer Phase 1.  REAL time: 25 secs 

Starting Placer Phase 2.
.
Placer score =  614592
Finished Placer Phase 2.  REAL time: 26 secs 

Total placer CPU time: 27 secs 

Dumping design to file mico8_demo.dir/5_1.ncd.

0 connections routed; 9286 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net pc_clk_c is not placed on
          one of the PIO sites which are dedicated for primary clocks.  This
          primary clock will be routed to a H-spine through general routing
          resource or be routed as secondary clock and may suffer from
          excessive delay or skew.
Completed router resource preassignment. Real time: 32 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
9286 successful; 0 unrouted; (0) real time: 41 secs 
Dumping design to file mico8_demo.dir/5_1.ncd.
Total CPU time 40 secs 
Total REAL time: 41 secs 
Completely routed.
End of route.  9286 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.
Timing score: 0 

Total REAL time to completion: 42 secs 


All signals are completely routed.


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