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Block ext_io_din_11_2 was optimized away.
Block ext_io_din_10_3 was optimized away.
Block ext_io_din_10_4 was optimized away.
Block ext_io_din_10_5 was optimized away.
Block ext_io_din_10_6 was optimized away.
Block ext_io_din_10_7 was optimized away.
Block ext_io_din_12_0 was optimized away.
Block ext_io_din_12_1 was optimized away.
Block ext_io_din_12_2 was optimized away.
Block ext_io_din_11_3 was optimized away.
Page 8
Design: isp8_top_system Date: 07/21/05 15:03:10
Removed logic (cont)
--------------------
Block ext_io_din_11_4 was optimized away.
Block ext_io_din_11_5 was optimized away.
Block ext_io_din_11_6 was optimized away.
Block ext_io_din_11_7 was optimized away.
Block ext_io_din_13_0 was optimized away.
Block ext_io_din_13_1 was optimized away.
Block ext_io_din_13_2 was optimized away.
Block ext_io_din_12_3 was optimized away.
Block ext_io_din_12_4 was optimized away.
Block ext_io_din_12_5 was optimized away.
Block ext_io_din_12_6 was optimized away.
Block ext_io_din_12_7 was optimized away.
Block ext_io_din_14_0 was optimized away.
Block ext_io_din_14_1 was optimized away.
Block ext_io_din_14_2 was optimized away.
Block ext_io_din_13_3 was optimized away.
Block ext_io_din_13_4 was optimized away.
Block ext_io_din_13_5 was optimized away.
Block ext_io_din_13_6 was optimized away.
Block ext_io_din_13_7 was optimized away.
Block U1_test_register/tst_regctl_i was optimized away.
Block U1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/AND2_0 was optimized away.
Block U1_isp8/u1_isp8_io_cntl/u1_isp8_spmem/INV_addr4 was optimized away.
Block U1_isp8/u1_isp8_rfmem/INV_waddr4 was optimized away.
Block GND was optimized away.
Block U1_led_decoder/VCC was optimized away.
Block U1_test_register/GND was optimized away.
Block U1_isp8/u1_isp8_flow_cntl/GND was optimized away.
Block U1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/GND was optimized away.
Block U1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/VCC was optimized away.
Block U1_isp8/u1_isp8_io_cntl/u1_isp8_spmem/VCC was optimized away.
Block U1_isp8/u1_isp8_prom/GND was optimized away.
Block U1_isp8/u1_isp8_rfmem/VCC was optimized away.
Symbol Cross Reference
----------------------
SLICE_0 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/stack_ptr1_0_F1,
U1_isp8/u1_isp8_flow_cntl/stack_ptr1_0_F2,
U1_isp8/u1_isp8_flow_cntl/stack_ptr1_0_inst_CB2
SLICE_1 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/pc_int_1_add1_0
SLICE_2 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/pc_int_1_add9_8
SLICE_3 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/pc_int_1_add7_6
SLICE_4 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/pc_int_1_add5_4
SLICE_5 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/pc_int_1_add3_2
SLICE_6 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/stack_ptr3_2_F1,
U1_isp8/u1_isp8_flow_cntl/stack_ptr3_2_F2,
U1_isp8/u1_isp8_flow_cntl/stack_ptr3_2_inst_CB2
SLICE_7 (PFU) covers blocks: U1_isp8/u1_isp8_alu/u1_addsub8/u4_as
SLICE_8 (PFU) covers blocks: U1_isp8/u1_isp8_alu/u1_addsub8/u1_as
SLICE_9 (PFU) covers blocks: U1_isp8/u1_isp8_alu/u1_addsub8/u2_as
SLICE_10 (PFU) covers blocks: U1_isp8/u1_isp8_alu/u1_addsub8/u3_as
SLICE_11 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_1_3/RAM0
SLICE_12 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_1_3/RAM1
SLICE_13 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_0_0/RAM0
SLICE_14 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_0_0/RAM1
Page 9
Design: isp8_top_system Date: 07/21/05 15:03:10
Symbol Cross Reference (cont)
-----------------------------
SLICE_15 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_0_1/RAM0
SLICE_16 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_0_1/RAM1
SLICE_17 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_0_2/RAM0
SLICE_18 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_0_2/RAM1
SLICE_19 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_0_3/RAM0
SLICE_20 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_0_3/RAM1
SLICE_21 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_1_0/RAM0
SLICE_22 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_1_0/RAM1
SLICE_23 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_1_1/RAM0
SLICE_24 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_1_1/RAM1
SLICE_25 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_1_2/RAM0
SLICE_26 (PFU) covers blocks: U1_isp8/u1_isp8_rfmem/mem_1_2/RAM1
SLICE_27 (PFU) covers blocks: U1_isp8/u1_isp8_io_cntl/u1_isp8_spmem/mem_0_0
SLICE_28 (PFU) covers blocks: U1_isp8/u1_isp8_io_cntl/u1_isp8_spmem/mem_0_1
SLICE_29 (PFU) covers blocks: U1_isp8/u1_isp8_io_cntl/u1_isp8_spmem/mem_0_2
SLICE_30 (PFU) covers blocks: U1_isp8/u1_isp8_io_cntl/u1_isp8_spmem/mem_0_3
SLICE_31 (PFU) covers blocks: U1_isp8/u1_isp8_io_cntl/u1_isp8_spmem/mem_1_0
SLICE_32 (PFU) covers blocks: U1_isp8/u1_isp8_io_cntl/u1_isp8_spmem/mem_1_1
SLICE_33 (PFU) covers blocks: U1_isp8/u1_isp8_io_cntl/u1_isp8_spmem/mem_1_2
SLICE_34 (PFU) covers blocks: U1_isp8/u1_isp8_io_cntl/u1_isp8_spmem/mem_1_3
SLICE_35 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_4
SLICE_36 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0
SLICE_37 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_1
SLICE_38 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2
SLICE_39 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_3
SLICE_40 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/addr_cyc_iZ0,
U1_isp8/u1_isp8_flow_cntl/addr_cycZ0
SLICE_41 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/G_54_0,
U1_isp8/u1_isp8_flow_cntl/carry_flag
SLICE_43 (PFU) covers blocks: U1_isp8/din_rd1_5_i_0, U1_isp8/din_rd1_5_i_1,
U1_isp8/din_rd1_0, U1_isp8/din_rd1_1
SLICE_44 (PFU) covers blocks: U1_isp8/din_rd1_5_i_2, U1_isp8/din_rd1_5_i_3,
U1_isp8/din_rd1_2, U1_isp8/din_rd1_3
SLICE_45 (PFU) covers blocks: U1_isp8/din_rd1_5_i_4, U1_isp8/din_rd1_5_i_5,
U1_isp8/din_rd1_4, U1_isp8/din_rd1_5
SLICE_46 (PFU) covers blocks: U1_isp8/din_rd1_5_i_6, U1_isp8/din_rd1_5_i_7,
U1_isp8/din_rd1_6, U1_isp8/din_rd1_7
SLICE_47 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/addr_jmp_reg_0,
U1_isp8/u1_isp8_flow_cntl/addr_jmp_reg_1
SLICE_48 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/addr_jmp_reg_2,
U1_isp8/u1_isp8_flow_cntl/addr_jmp_reg_3
SLICE_49 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/addr_jmp_reg_4,
U1_isp8/u1_isp8_flow_cntl/addr_jmp_reg_5
SLICE_50 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/addr_jmp_reg_6,
U1_isp8/u1_isp8_flow_cntl/addr_jmp_reg_7
SLICE_52 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/G_65_0_a2/GATE,
U1_isp8/u1_isp8_flow_cntl/G_65_0_a2_blut,
U1_isp8/u1_isp8_flow_cntl/G_65_0_a2_alut,
U1_isp8/u1_isp8_flow_cntl/br_enb_reg
SLICE_53 (PFU) covers blocks: U1_isp8/u1_isp8_alu/dout_alu_1_iv_0_0,
U1_isp8/u1_isp8_alu/dout_alu_1_iv_0_1,
U1_isp8/u1_isp8_flow_cntl/dout_alu_reg_0,
U1_isp8/u1_isp8_flow_cntl/dout_alu_reg_1
SLICE_54 (PFU) covers blocks: U1_isp8/u1_isp8_alu/dout_alu_1_iv_0_2,
U1_isp8/u1_isp8_alu/dout_alu_1_iv_0_3,
U1_isp8/u1_isp8_flow_cntl/dout_alu_reg_2,
Page 10
Design: isp8_top_system Date: 07/21/05 15:03:10
Symbol Cross Reference (cont)
-----------------------------
U1_isp8/u1_isp8_flow_cntl/dout_alu_reg_3
SLICE_55 (PFU) covers blocks: U1_isp8/u1_isp8_alu/dout_alu_1_iv_0_4,
U1_isp8/u1_isp8_alu/dout_alu_1_iv_0_5,
U1_isp8/u1_isp8_flow_cntl/dout_alu_reg_4,
U1_isp8/u1_isp8_flow_cntl/dout_alu_reg_5
SLICE_56 (PFU) covers blocks: U1_isp8/u1_isp8_alu/dout_alu_1_iv_0_6,
U1_isp8/u1_isp8_alu/dout_alu_1_iv_0_7,
U1_isp8/u1_isp8_flow_cntl/dout_alu_reg_6,
U1_isp8/u1_isp8_flow_cntl/dout_alu_reg_7
SLICE_57 (PFU) covers blocks: U1_isp8/u1_isp8_idec/clri_0_0_a2,
U1_isp8/u1_isp8_idec/addc_0_0_o2, U1_isp8/u1_isp8_flow_cntl/ie_flag
SLICE_58 (PFU) covers blocks: U1_test_register/intrZ0,
U1_isp8/u1_isp8_flow_cntl/intr_reg0
SLICE_59 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/G_44Z0Z_0,
U1_isp8/u1_isp8_flow_cntl/G_24Z0Z_0, U1_isp8/u1_isp8_flow_cntl/pc_0,
U1_isp8/u1_isp8_flow_cntl/pc_1
SLICE_60 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/G_27Z0Z_0,
U1_isp8/u1_isp8_flow_cntl/G_30Z0Z_0, U1_isp8/u1_isp8_flow_cntl/pc_2,
U1_isp8/u1_isp8_flow_cntl/pc_3
SLICE_61 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/G_50Z0Z_0,
U1_isp8/u1_isp8_flow_cntl/G_47Z0Z_0, U1_isp8/u1_isp8_flow_cntl/pc_4,
U1_isp8/u1_isp8_flow_cntl/pc_5
SLICE_62 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/G_35Z0Z_0,
U1_isp8/u1_isp8_flow_cntl/G_38Z0Z_0, U1_isp8/u1_isp8_flow_cntl/pc_6,
U1_isp8/u1_isp8_flow_cntl/pc_7
SLICE_63 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/G_41Z0Z_0,
U1_isp8/u1_isp8_flow_cntl/G_63_0, U1_isp8/u1_isp8_flow_cntl/pc_8
SLICE_64 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/G,
U1_isp8/u1_isp8_flow_cntl/pecz_reg
SLICE_65 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/pushed_carry
SLICE_66 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/pushed_zero
SLICE_67 (PFU) covers blocks: U1_isp8/u1_isp8_idec/iret_0_0_a2_0_a2_1,
U1_isp8/u1_isp8_flow_cntl/G_54_0_0, U1_isp8/u1_isp8_flow_cntl/ret_reg
SLICE_68 (PFU) covers blocks: U1_isp8/u1_isp8_flow_cntl/G_60_0,
U1_isp8/u1_isp8_idec/update_cz_0_i_0, U1_isp8/u1_isp8_flow_cntl/zero_flag
SLICE_69 (PFU) covers blocks: U1_isp8/u1_isp8_io_cntl/int_mem_wr_3_0_0_a2,
U1_isp8/din_rd_i_1, U1_isp8/u1_isp8_io_cntl/int_mem_wr
SLICE_70 (PFU) covers blocks: U1_isp8/wren_alu_rd_3_0_0_0,
U1_isp8/wren_alu_rd_3_0_0_0_a2, U1_isp8/wren_alu_rd
SLICE_71 (PFU) covers blocks: U1_isp8/wren_il_rd_3_0_0_o2, U1_isp8/wren_il_rd
SLICE_72 (PFU) covers blocks: U1_orcastra_inf/load_h/load_ns_i_0_a2Z0Z_1,
U1_orcastra_inf/load_en
SLICE_73 (PFU) covers blocks: U1_orcastra_inf/load_h/load_ns_0_0_0,
U1_orcastra_inf/load_h/load_ns_i_0_1, U1_orcastra_inf/load_h/load_0,
U1_orcastra_inf/load_h/load_1
SLICE_74 (PFU) covers blocks: U1_orcastra_inf/G_18, U1_orcastra_inf/G_11,
U1_orcastra_inf/load_reg_0, U1_orcastra_inf/load_reg_1
SLICE_75 (PFU) covers blocks: U1_orcastra_inf/G_12, U1_orcastra_inf/G_13,
U1_orcastra_inf/load_reg_2, U1_orcastra_inf/load_reg_3
SLICE_76 (PFU) covers blocks: U1_orcastra_inf/G_14, U1_orcastra_inf/G_15,
U1_orcastra_inf/load_reg_4, U1_orcastra_inf/load_reg_5
SLICE_77 (PFU) covers blocks: U1_orcastra_inf/G_16, U1_orcastra_inf/load_reg_6
SLICE_78 (PFU) covers blocks: U1_orcastra_inf/read_data_0,
U1_orcastra_inf/read_data_1
SLICE_79 (PFU) covers blocks: U1_orcastra_inf/read_data_2,
U1_orcastra_inf/read_data_3
Page 11
Design: isp8_top_system Date: 07/21/05 15:03:10
Symbol Cross Reference (cont)
-----------------------------
SLICE_80 (PFU) covers blocks: U1_orcastra_inf/read_data_4,
U1_orcastra_inf/read_data_5
SLICE_81 (PFU) covers blocks: U1_orcastra_inf/read_data_6,
U1_orcastra_inf/read_data_7
SLICE_82 (PFU) covers blocks: U1_orcastra_inf/ad_reg_8, U1_orcastra_inf/ad_reg_9
SLICE_83 (PFU) covers blocks: U1_orcastra_inf/ad_reg_10,
U1_orcastra_inf/ad_reg_11
SLICE_84 (PFU) covers blocks: U1_orcastra_inf/ad_reg_16,
U1_orcastra_inf/ad_reg_17
SLICE_85 (PFU) covers blocks:
U1_orcastra_inf/tst_timegen_h/tst_timegen_ns_0_0_0,
U1_orcastra_inf/tst_timegen_h/tst_timegen_ns_i_0_1,
U1_orcastra_inf/tst_timegen_h/tst_timegenZ0Z_0,
U1_orcastra_inf/tst_timegen_h/tst_timegenZ0Z_1
SLICE_86 (PFU) covers blocks: U1_orcastra_inf/wr_only
SLICE_87 (PFU) covers blocks: U1_test_register/G_998, U1_test_register/G_999,
U1_test_register/EXT_IO_DIN_REG_0, U1_test_register/EXT_IO_DIN_REG_1
SLICE_88 (PFU) covers blocks: U1_test_register/G_989, U1_test_register/G_997,
U1_test_register/EXT_IO_DIN_REG_2, U1_test_register/EXT_IO_DIN_REG_3
SLICE_89 (PFU) covers blocks: U1_test_register/G_1016, U1_test_register/G_996,
U1_test_register/EXT_IO_DIN_REG_4, U1_test_register/EXT_IO_DIN_REG_5
SLICE_90 (PFU) covers blocks: U1_test_register/G_988, U1_test_register/G_1000,
U1_test_register/EXT_IO_DIN_REG_6, U1_test_register/EXT_IO_DIN_REG_7
SLICE_91 (PFU) covers blocks: U1_test_register/G_1082, U1_test_register/G_1020,
U1_test_register/INTR_REG_0, U1_test_register/INTR_REG_1
SLICE_92 (PFU) covers blocks: U1_test_register/G_1007, U1_test_register/G_1010,
U1_test_register/INTR_REG_2, U1_test_register/INTR_REG_3
SLICE_93 (PFU) covers blocks: U1_test_register/G_990_0, U1_test_register/G_1043,
U1_test_register/INTR_REG_4, U1_test_register/INTR_REG_5
SLICE_94 (PFU) covers blocks: U1_test_register/G_1023, U1_test_register/G_1013,
U1_test_register/INTR_REG_6, U1_test_register/INTR_REG_7
SLICE_95 (PFU) covers blocks: U1_test_register/STORE_REGS_35,
U1_test_register/STORE_REGS_36, U1_test_register/STORE_REGS_0,
U1_test_register/STORE_REGS_1
SLICE_96 (PFU) covers blocks: U1_test_register/STORE_REGS_37,
U1_test_register/STORE_REGS_38, U1_test_register/STORE_REGS_2,
U1_test_register/STORE_REGS_3
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