📄 mico8_demo.mrp
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Lattice Mapping Report File for Design 'isp8_top_system'
Design Information
------------------
Command line: C:\ispTOOLS5_0\ispfpga\bin\nt\map.exe -a mg5g00 -p LFXP10C -t
FPBGA388 -s 5 mico8_demo.ngd -o mico8_demo_map.ncd -mp mico8_demo.mrp
mico8_demo.prf
Target Vendor: LATTICE
Target Device: LFXP10CFPBGA388
Target Speed: 5
Mapper: mg5g00, version: ispLever_v50_Production_Build (40)
Mapped on: 07/21/05 15:03:10
Design Summary
--------------
Number of registers: 455
PFU registers: 455
PIO registers: 0
Number of SLICEs: 1230 out of 4864 (25%)
SLICEs(logic): 1201 out of 3648 (33%)
SLICEs(logic/RAM): 29 out of 1216 (2%)
As RAM: 29
As Logic: 0
Number of logic LUT4s: 2190
Number of distributed RAM: 29 (58 LUT4s)
Number of ripple logic: 11 (22 LUT4s)
Number of shift registers: 0
Total number of LUT4s: 2270
Number of external PIOs: 26 out of 244 (11%)
Number of PIO IDDR/ODDR: 0
Number of 3-state buffers: 0
Number of PLLs: 0 out of 4 (0%)
Number of Block RAMs: 1 out of 24 (4%)
Number of GSRs: 1 out of 1 (100%)
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 2
Net tst_sys_clk_c: 249 loads, 249 rising, 0 falling (Driver: PIO
tst_sys_clk )
Net pc_clk_c: 18 loads, 0 rising, 18 falling (Driver: PIO pc_clk )
Number of Clock Enables: 16
Net ext_io_wr: 4 loads, 4 LSLICEs
Net U1_isp8/addr_cyc: 8 loads, 7 LSLICEs
Net U1_isp8/data_cyc: 5 loads, 5 LSLICEs
Net U1_isp8/u1_isp8_flow_cntl/G_57_0_a2Z0Z_0: 2 loads, 2 LSLICEs
Net U1_isp8/u1_isp8_flow_cntl/un1_iret_1_0_i_aZ0Z2: 1 loads, 1 LSLICEs
Net U1_isp8/u1_isp8_flow_cntl/push_enb_cz: 2 loads, 2 LSLICEs
Net U1_isp8/seti_0_0_a2: 1 loads, 1 LSLICEs
Net U1_test_register/N_9762_r24: 31 loads, 31 LSLICEs
Page 1
Design: isp8_top_system Date: 07/21/05 15:03:10
Design Summary (cont)
---------------------
Net U1_test_register/GZ0Z_1149: 4 loads, 4 LSLICEs
Net U1_test_register/GZ0Z_1163: 4 loads, 4 LSLICEs
Net U1_test_register/tst_regctlZ0: 2 loads, 2 LSLICEs
Net U1_test_register/tst_rdZ0: 4 loads, 4 LSLICEs
Net U1_orcastra_inf/GZ0Z_10: 1 loads, 1 LSLICEs
Net U1_orcastra_inf/un1_pc_ack_1_sqmuxa_1_0Z0Z_0: 1 loads, 1 LSLICEs
Net U1_orcastra_inf/un1_tst_sel_0_sqmuxa_1_0_iZ0: 1 loads, 1 LSLICEs
Net U1_orcastra_inf/read_data6: 4 loads, 4 LSLICEs
Number of LSRs: 7
Net U1_isp8/u1_isp8_rfmem/dec_wre7: 8 loads, 8 LSLICEs
Net U1_isp8/u1_isp8_rfmem/dec_wre3: 8 loads, 8 LSLICEs
Net U1_isp8/u1_isp8_io_cntl/u1_isp8_spmem/dec_wre3: 4 loads, 4 LSLICEs
Net U1_isp8/u1_isp8_io_cntl/u1_isp8_spmem/dec_wre7: 4 loads, 4 LSLICEs
Net U1_isp8/u1_isp8_flow_cntl/N_9_i: 5 loads, 5 LSLICEs
Net tst_addr_3: 3 loads, 3 LSLICEs
Net tst_addr_2: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net tst_addr_5: 206 loads
Net tst_addr_4: 193 loads
Net U1_test_register/N_8923_i_0_r0: 100 loads
Net U1_test_register/N_8923_i_0_r5: 100 loads
Net U1_test_register/N_9903_r2: 100 loads
Net U1_test_register/rst_test_reg_r1: 100 loads
Net tst_addr_3: 76 loads
Net U1_test_register/N_9903_r4: 72 loads
Net U1_test_register/rst_test_reg_r3: 72 loads
Net tst_addr_2: 66 loads
IO (PIO) Attributes
-------------------
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| pc_reset_out | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| tst_sys_clk | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| light_on_7 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| light_on_6 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| light_on_5 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| light_on_4 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| light_on_3 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| light_on_2 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| light_on_1 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| light_on_0 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Page 2
Design: isp8_top_system Date: 07/21/05 15:03:10
IO (PIO) Attributes (cont)
--------------------------
| led_out_6 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| led_out_5 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| led_out_4 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| led_out_3 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| led_out_2 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| led_out_1 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| led_out_0 | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| pc_err | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| pc_retry | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| pc_ack | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| pc_dataout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| pc_reset | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| pc_clk | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| pc_ready | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| pc_datain | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| reset_n | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Removed logic
-------------
Block VCC undriven or does not drive anything - clipped.
Block U1_orcastra_inf/GND undriven or does not drive anything - clipped.
Block U1_orcastra_inf/tst_timegen_h/GND undriven or does not drive anything -
clipped.
Block U1_orcastra_inf/load_h/GND undriven or does not drive anything - clipped.
Block U1_led_decoder/GND undriven or does not drive anything - clipped.
Block U1_isp8/GND undriven or does not drive anything - clipped.
Block U1_isp8/u1_isp8_idec/GND undriven or does not drive anything - clipped.
Block U1_isp8/u1_isp8_alu/GND undriven or does not drive anything - clipped.
Block U1_isp8/u1_isp8_flow_cntl/VCC undriven or does not drive anything -
clipped.
Block U1_isp8/u1_isp8_io_cntl/GND undriven or does not drive anything - clipped.
Block U1_isp8/u1_isp8_io_cntl/u1_isp8_spmem/GND undriven or does not drive
anything - clipped.
Block U1_isp8/u1_isp8_rfmem/GND undriven or does not drive anything - clipped.
Signal pc_clk_c_iZ0 was merged into signal pc_clk_c
Signal ext_io_din_0Z0Z_0 was merged into signal ext_io_dinZ0Z_0
Signal ext_io_din_0Z0Z_1 was merged into signal ext_io_dinZ0Z_1
Signal ext_io_din_0Z0Z_2 was merged into signal ext_io_dinZ0Z_2
Signal ext_io_din_0Z0Z_3 was merged into signal ext_io_dinZ0Z_3
Page 3
Design: isp8_top_system Date: 07/21/05 15:03:10
Removed logic (cont)
--------------------
Signal ext_io_din_0Z0Z_4 was merged into signal ext_io_dinZ0Z_4
Signal ext_io_din_0Z0Z_5 was merged into signal ext_io_dinZ0Z_5
Signal ext_io_din_0Z0Z_6 was merged into signal ext_io_dinZ0Z_6
Signal ext_io_din_0Z0Z_7 was merged into signal ext_io_dinZ0Z_7
Signal ext_io_din_1Z0Z_0 was merged into signal ext_io_dinZ0Z_0
Signal ext_io_din_1Z0Z_1 was merged into signal ext_io_dinZ0Z_1
Signal ext_io_din_1Z0Z_2 was merged into signal ext_io_dinZ0Z_2
Signal ext_io_din_1Z0Z_3 was merged into signal ext_io_dinZ0Z_3
Signal ext_io_din_1Z0Z_4 was merged into signal ext_io_dinZ0Z_4
Signal ext_io_din_1Z0Z_5 was merged into signal ext_io_dinZ0Z_5
Signal ext_io_din_1Z0Z_6 was merged into signal ext_io_dinZ0Z_6
Signal ext_io_din_1Z0Z_7 was merged into signal ext_io_dinZ0Z_7
Signal ext_io_din_2Z0Z_0 was merged into signal ext_io_dinZ0Z_0
Signal ext_io_din_2Z0Z_1 was merged into signal ext_io_dinZ0Z_1
Signal ext_io_din_2Z0Z_2 was merged into signal ext_io_dinZ0Z_2
Signal ext_io_din_2Z0Z_3 was merged into signal ext_io_dinZ0Z_3
Signal ext_io_din_2Z0Z_4 was merged into signal ext_io_dinZ0Z_4
Signal ext_io_din_2Z0Z_5 was merged into signal ext_io_dinZ0Z_5
Signal ext_io_din_2Z0Z_6 was merged into signal ext_io_dinZ0Z_6
Signal ext_io_din_2Z0Z_7 was merged into signal ext_io_dinZ0Z_7
Signal ext_io_din_3Z0Z_0 was merged into signal ext_io_dinZ0Z_0
Signal ext_io_din_3Z0Z_1 was merged into signal ext_io_dinZ0Z_1
Signal ext_io_din_3Z0Z_2 was merged into signal ext_io_dinZ0Z_2
Signal ext_io_din_4Z0Z_0 was merged into signal ext_io_dinZ0Z_0
Signal ext_io_din_4Z0Z_1 was merged into signal ext_io_dinZ0Z_1
Signal ext_io_din_4Z0Z_2 was merged into signal ext_io_dinZ0Z_2
Signal ext_io_din_3Z0Z_3 was merged into signal ext_io_dinZ0Z_3
Signal ext_io_din_3Z0Z_4 was merged into signal ext_io_dinZ0Z_4
Signal ext_io_din_3Z0Z_5 was merged into signal ext_io_dinZ0Z_5
Signal ext_io_din_3Z0Z_6 was merged into signal ext_io_dinZ0Z_6
Signal ext_io_din_3Z0Z_7 was merged into signal ext_io_dinZ0Z_7
Signal ext_io_din_5Z0Z_0 was merged into signal ext_io_dinZ0Z_0
Signal ext_io_din_5Z0Z_1 was merged into signal ext_io_dinZ0Z_1
Signal ext_io_din_5Z0Z_2 was merged into signal ext_io_dinZ0Z_2
Signal ext_io_din_4Z0Z_3 was merged into signal ext_io_dinZ0Z_3
Signal ext_io_din_4Z0Z_4 was merged into signal ext_io_dinZ0Z_4
Signal ext_io_din_4Z0Z_5 was merged into signal ext_io_dinZ0Z_5
Signal ext_io_din_4Z0Z_6 was merged into signal ext_io_dinZ0Z_6
Signal ext_io_din_4Z0Z_7 was merged into signal ext_io_dinZ0Z_7
Signal ext_io_din_6Z0Z_0 was merged into signal ext_io_dinZ0Z_0
Signal ext_io_din_6Z0Z_1 was merged into signal ext_io_dinZ0Z_1
Signal ext_io_din_6Z0Z_2 was merged into signal ext_io_dinZ0Z_2
Signal ext_io_din_5Z0Z_3 was merged into signal ext_io_dinZ0Z_3
Signal ext_io_din_5Z0Z_4 was merged into signal ext_io_dinZ0Z_4
Signal ext_io_din_5Z0Z_5 was merged into signal ext_io_dinZ0Z_5
Signal ext_io_din_5Z0Z_6 was merged into signal ext_io_dinZ0Z_6
Signal ext_io_din_5Z0Z_7 was merged into signal ext_io_dinZ0Z_7
Signal ext_io_din_7Z0Z_0 was merged into signal ext_io_dinZ0Z_0
Signal ext_io_din_7Z0Z_1 was merged into signal ext_io_dinZ0Z_1
Signal ext_io_din_7Z0Z_2 was merged into signal ext_io_dinZ0Z_2
Signal ext_io_din_6Z0Z_3 was merged into signal ext_io_dinZ0Z_3
Signal ext_io_din_6Z0Z_4 was merged into signal ext_io_dinZ0Z_4
Signal ext_io_din_6Z0Z_5 was merged into signal ext_io_dinZ0Z_5
Signal ext_io_din_6Z0Z_6 was merged into signal ext_io_dinZ0Z_6
Signal ext_io_din_6Z0Z_7 was merged into signal ext_io_dinZ0Z_7
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