mico8_demo.twr

简单的8位CPU

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Lattice TRACE Report, Version ispLever_v50_Production_Build (40)
Thu Jul 21 15:03:59 2005

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2005 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -o checkpnt.twr mico8_demo.ncd mico8_demo.prf 
Design file:     mico8_demo.ncd
Preference file: mico8_demo.prf
Device,speed:    LFXP10C,5
Report level:    verbose report, limited to 1 item per preference
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WARNING - trce: No timing preferences found, doing default enumeration. 
14 potential circuit loops found in timing analysis. 
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: Default path enumeration
            4096 items scored, 0 timing errors detected.
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Report:   17.857ns delay U1_isp8/u1_isp8_prom/prom_0_0_0 to SLICE_46 (17.728ns delay and 0.129ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     3.476 EBR_R10C13.CLK to EBR_R10C13.DO5 U1_isp8/u1_isp8_prom/prom_0_0_0 (from tst_sys_clk_c)
ROUTE        20     3.051 EBR_R10C13.DO5 to     R14C14A.C1 U1_isp8/DO5
RAM_DEL     ---     0.300     R14C14A.C1 to     R14C14A.F1 SLICE_25
ROUTE         1     1.213     R14C14A.F1 to     R11C14C.D0 U1_isp8/u1_isp8_rfmem/mdL0_1_5
CTOF_DEL    ---     0.300     R11C14C.D0 to     R11C14C.F0 SLICE_528
ROUTE         5     1.981     R11C14C.F0 to      R7C15A.C0 U1_isp8/dout_rb_2
CTOF_DEL    ---     0.300      R7C15A.C0 to      R7C15A.F0 SLICE_541
ROUTE         3     1.629      R7C15A.F0 to      R8C14B.B0 U1_isp8/u1_isp8_alu/dout_alu_1_iv_0_m2Z0Z_2
B0TOFCO_DE  ---     0.726      R8C14B.B0 to     R8C14B.FCO SLICE_9
ROUTE         1     0.000     R8C14B.FCO to     R8C14C.FCI U1_isp8/u1_isp8_alu/u1_addsub8/out_c2
FCITOFCO_D  ---     0.103     R8C14C.FCI to     R8C14C.FCO SLICE_10
ROUTE         1     0.000     R8C14C.FCO to     R8C14D.FCI U1_isp8/u1_isp8_alu/u1_addsub8/out_c3
TLATCH_DEL  ---     0.774     R8C14D.FCI to      R8C14D.Q1 SLICE_7
ROUTE         1     0.755      R8C14D.Q1 to      R8C12A.D1 U1_isp8/u1_isp8_alu/data_add_7
CTOF_DEL    ---     0.300      R8C12A.D1 to      R8C12A.F1 SLICE_548
ROUTE         1     0.793      R8C12A.F1 to      R8C13D.D1 U1_isp8/u1_isp8_alu/N_395
CTOF_DEL    ---     0.300      R8C13D.D1 to      R8C13D.F1 SLICE_56
ROUTE         2     1.427      R8C13D.F1 to      R9C15D.A1 U1_isp8/un1_U1_isp8_1_i_7
CTOF_DEL    ---     0.300      R9C15D.A1 to      R9C15D.F1 SLICE_46
ROUTE         1     0.000      R9C15D.F1 to     R9C15D.DI1 U1_isp8/N_245_i (to tst_sys_clk_c)
                  --------
                   17.728   (38.8% logic, 61.2% route), 10 logic levels.

Report:   56.000MHz is the maximum frequency for this preference.


================================================================================
Preference: Default net enumeration
            2694 items scored, 0 timing errors detected.
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Report:    6.456ns maximum delay on pc_clk_c

           Delays             Connection(s)
           6.456ns         W8.PADDI to R25C31B.CLK     
           6.456ns         W8.PADDI to R28C29D.CLK     
           6.456ns         W8.PADDI to R19C30D.CLK     
           6.456ns         W8.PADDI to R26C15D.CLK     
           6.456ns         W8.PADDI to R26C34D.CLK     
           6.456ns         W8.PADDI to R26C34B.CLK     
           6.456ns         W8.PADDI to R22C27B.CLK     
           6.456ns         W8.PADDI to R26C22C.CLK     
           6.456ns         W8.PADDI to R14C27B.CLK     
           6.456ns         W8.PADDI to R24C28D.CLK     
           6.456ns         W8.PADDI to R23C33B.CLK     
           6.456ns         W8.PADDI to R25C34C.CLK     
           6.456ns         W8.PADDI to R25C34D.CLK     
           6.456ns         W8.PADDI to R23C34C.CLK     
           6.456ns         W8.PADDI to R23C33C.CLK     
           6.456ns         W8.PADDI to R22C33D.CLK     
           6.456ns         W8.PADDI to R23C33A.CLK     
           6.456ns         W8.PADDI to R22C33A.CLK     
           3.825ns         W8.PADDI to R22C36D.D1      
           3.825ns         W8.PADDI to R22C36D.D0      

Report:    6.456ns is the maximum delay for this preference.

Report Summary
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----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
Default path enumeration                |    0.000 MHz|   56.000 MHz|     0
                                        |             |             |
Default net enumeration                 |     0.000 ns|     6.456 ns|     0
                                        |             |             |
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All preferences were met.


Timing summary:
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Timing errors: 0  Score: 0

Constraints cover 25708 paths, 2694 nets, and 9256 connections (99.7% coverage)

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