isp8.srr

简单的8位CPU

#Program: Synplify 8.0B
#OS: Windows_NT

$ Start of Compile
#Tue Jun 28 17:26:38 2005

Synplicity Verilog Compiler, version 3.0.0, Build 286R, built Jan 13 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v"
@I::"C:\Anto_2005\Reference_Design\isp8\anto\source\top\isp8_top_test_system.v"
@I::"C:\Anto_2005\Reference_Design\isp8\source\isp8.v"
@I:"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":"C:\Anto_2005\Reference_Design\isp8\source\config1\isp8_cfg.v"
@N: CG347 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":342:31:342:43|Read parallel_case directive 
@N: CG334 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":364:12:364:24|Read directive translate_off 
@N: CG333 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":433:12:433:23|Read directive translate_on 
@N: CG347 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":752:31:752:43|Read parallel_case directive 
@N: CG347 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":771:31:771:43|Read parallel_case directive 
@N: CG347 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":790:31:790:43|Read parallel_case directive 
@N: CG347 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":804:31:804:43|Read parallel_case directive 
@N: CG347 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":852:31:852:43|Read parallel_case directive 
@N: CG347 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1053:34:1053:46|Read parallel_case directive 
@N: CG347 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1062:53:1062:65|Read parallel_case directive 
Verilog syntax check successful!
Selecting top level module isp8_top_test_system
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\anto\source\top\isp8_top_test_system.v":39:13:39:15|Reference to undefined module orcastra_inf
@N: CG364 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":1:7:1:19|Synthesizing module test_register

@W: CG133 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":53:8:53:19|No assignment to rst_tst_regs
@W: CG133 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":54:8:54:16|No assignment to cpu_start
@W: CG133 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":79:9:79:20|No assignment to tst_type_reg
@W: CG133 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":82:5:82:19|No assignment to status_user_reg
@W: CL112 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":281:0:281:5|Feedback mux created for signal intr_addr. Did you forget the set/reset assignment for this signal?
@W: CL112 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":281:0:281:5|Feedback mux created for signal ext_io_din_addr. Did you forget the set/reset assignment for this signal?
@N: CL177 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":149:0:149:5|Sharing sequential element tst_regctl.
@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":38:12:38:23|Input port bit <11> of tst_sys_addr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":38:12:38:23|Input port bit <10> of tst_sys_addr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":38:12:38:23|Input port bit <9> of tst_sys_addr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":38:12:38:23|Input port bit <8> of tst_sys_addr[17:0] is unused

@W: CL153 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":53:8:53:19|*Unassigned bits of rst_tst_regs have been referenced and are being tied to 0 - simulation mismatch possible
@W: CL153 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":54:8:54:16|*Unassigned bits of cpu_start have been referenced and are being tied to 0 - simulation mismatch possible
@W: CL157 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":50:12:50:21|*Output ext_io_din has undriven bits - a simulation mismatch is possible 
@W: CL157 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":51:8:51:11|*Output intr has undriven bits - a simulation mismatch is possible 
@W: CL157 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":52:12:52:20|*Output speed_out has undriven bits - a simulation mismatch is possible 
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":42:11:42:18|Input ext_addr is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":43:13:43:20|Input ext_dout is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":45:7:45:15|Input ext_io_wr is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":44:7:44:15|Input ext_io_rd is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":46:7:46:18|Input ext_intr_ack is unused
@N: CG364 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1112:7:1112:15|Synthesizing module isp8_idec

@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1175:13:1175:15|Input clk is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1176:13:1176:17|Input rst_n is unused
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1090:7:1090:11|Reference to undefined module FADSU2
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1095:7:1095:11|Reference to undefined module FADSU2
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1100:7:1100:11|Reference to undefined module FADSU2
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1105:7:1105:11|Reference to undefined module FADSU2
@N: CG364 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1074:7:1074:13|Synthesizing module addsub8

@W: CG141 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1090:7:1090:11|Creating black_box for FADSU2
Making port A0 a bidir
Making port A1 a bidir
Making port B0 a bidir
Making port B1 a bidir
Making port BCI a bidir
Making port CON a bidir
Making port BCO a bidir
Making port S0 a bidir
Making port S1 a bidir
@N: CG364 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":861:7:861:14|Synthesizing module isp8_alu

@W: CG133 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":921:13:921:21|No assignment to carry_int
@W:"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":927:13:927:24|No assignment to wire data_rb_comp

@W:"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1002:11:1002:16|No assignment to wire alu_op

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <13> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <12> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <11> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <10> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <9> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <8> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <7> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <6> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <5> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <4> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <3> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <2> of instr[17:0] is unused

@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":893:13:893:15|Input clk is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":894:13:894:17|Input rst_n is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":904:12:904:14|Input add is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":906:12:906:14|Input mov is unused