isp8_top_test_system.srs

简单的8位CPU

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.0.0, Build 286R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Tue Jul 05 14:46:53 2005
#
#
#OPTIONS:"|-fixsmult|-IC:\\Anto_2005\\Reference_Design\\isp8\\source\\config1\\|-IC:\\Anto_2005\\Reference_Design\\isp8\\anto\\test\\|-IC:\\Anto_2005\\Reference_Design\\isp8\\anto\\synthesis\\top\\|-IC:\\ispTOOLS5_0\\synpbase\\lib|-v2001|-autosm|-fid2|-sharing|on|-encrypt|-ui|-ram"
#CUR:"C:\\ispTOOLS5_0\\synpbase\\bin\\c_ver.exe":1105668864
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\dpram32x8.v":1118078947
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\dpram32x8.v":1118078947
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\prom.v":1118078947
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\prom.v":1118078947
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\test\\prom_init.v":1120599454
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\test\\prom_init.v":1120599454
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\test\\prom_init.v":1120599454
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\test\\prom_init.v":1120599454
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\test\\prom_init.v":1120599454
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\test\\prom_init.v":1120599454
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\source\\isp8.v":1120256545
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\source\\isp8.v":1120256545
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\source\\config1\\isp8_cfg.v":1120258105
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\source\\config1\\isp8_cfg.v":1120258105
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\spram32x8.v":1118078948
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\spram32x8.v":1118078948
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\spram16x8.v":1118078948
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\spram16x8.v":1118078948
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\spram16x9.v":1118078948
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\spram16x9.v":1118078948
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\spram16x10.v":1118078948
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\spram16x10.v":1118078948
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\xp.v":1118078949
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\models\\xp\\syn\\xp.v":1118078949
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\source\\test_register\\test_register.v":1120258635
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\source\\test_register\\test_register.v":1120258635
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\source\\orcastra_inf\\orcastra_inf.v":1120163353
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\source\\orcastra_inf\\orcastra_inf.v":1120163353
f "C:\Anto_2005\Reference_Design\isp8\models\xp\syn\dpram32x8.v"; # file 0
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\models\xp\syn\prom.v"; # file 1
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\anto\test\prom_init.v"; # file 2
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\anto\test\prom_init.v"; # file 3
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\anto\test\prom_init.v"; # file 4
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\source\isp8.v"; # file 5
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\source\config1\isp8_cfg.v"; # file 6
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram32x8.v"; # file 7
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x8.v"; # file 8
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x9.v"; # file 9
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v"; # file 10
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\models\xp\syn\xp.v"; # file 11
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v"; # file 12
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\anto\source\orcastra_inf\orcastra_inf.v"; # file 13
af .is_verilog 1;
@E
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Rj@@:44::.4:RPHMR4kM_00#_D#C_#j_JGlkNR_.k_M40_#0#_CDjJ_#lNkG_k.RM04_##0_CjD__l#Jk_GN4b;
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