isp8.tlg

简单的8位CPU

Selecting top level module isp8_top_test_system
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\anto\source\top\isp8_top_test_system.v":39:13:39:15|Reference to undefined module orcastra_inf
@N: CG364 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":1:7:1:19|Synthesizing module test_register

@W: CG133 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":53:8:53:19|No assignment to rst_tst_regs
@W: CG133 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":54:8:54:16|No assignment to cpu_start
@W: CG133 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":79:9:79:20|No assignment to tst_type_reg
@W: CG133 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":82:5:82:19|No assignment to status_user_reg
@W: CL112 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":281:0:281:5|Feedback mux created for signal intr_addr. Did you forget the set/reset assignment for this signal?
@W: CL112 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":281:0:281:5|Feedback mux created for signal ext_io_din_addr. Did you forget the set/reset assignment for this signal?
@N: CL177 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":149:0:149:5|Sharing sequential element tst_regctl.
@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":38:12:38:23|Input port bit <11> of tst_sys_addr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":38:12:38:23|Input port bit <10> of tst_sys_addr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":38:12:38:23|Input port bit <9> of tst_sys_addr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":38:12:38:23|Input port bit <8> of tst_sys_addr[17:0] is unused

@W: CL153 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":53:8:53:19|*Unassigned bits of rst_tst_regs have been referenced and are being tied to 0 - simulation mismatch possible
@W: CL153 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":54:8:54:16|*Unassigned bits of cpu_start have been referenced and are being tied to 0 - simulation mismatch possible
@W: CL157 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":50:12:50:21|*Output ext_io_din has undriven bits - a simulation mismatch is possible 
@W: CL157 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":51:8:51:11|*Output intr has undriven bits - a simulation mismatch is possible 
@W: CL157 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":52:12:52:20|*Output speed_out has undriven bits - a simulation mismatch is possible 
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":42:11:42:18|Input ext_addr is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":43:13:43:20|Input ext_dout is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":45:7:45:15|Input ext_io_wr is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":44:7:44:15|Input ext_io_rd is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v":46:7:46:18|Input ext_intr_ack is unused
@N: CG364 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1112:7:1112:15|Synthesizing module isp8_idec

@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1175:13:1175:15|Input clk is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1176:13:1176:17|Input rst_n is unused
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1090:7:1090:11|Reference to undefined module FADSU2
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1095:7:1095:11|Reference to undefined module FADSU2
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1100:7:1100:11|Reference to undefined module FADSU2
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1105:7:1105:11|Reference to undefined module FADSU2
@N: CG364 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1074:7:1074:13|Synthesizing module addsub8

@W: CG141 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1090:7:1090:11|Creating black_box for FADSU2
Making port A0 a bidir
Making port A1 a bidir
Making port B0 a bidir
Making port B1 a bidir
Making port BCI a bidir
Making port CON a bidir
Making port BCO a bidir
Making port S0 a bidir
Making port S1 a bidir
@N: CG364 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":861:7:861:14|Synthesizing module isp8_alu

@W: CG133 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":921:13:921:21|No assignment to carry_int
@W:"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":927:13:927:24|No assignment to wire data_rb_comp

@W:"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":1002:11:1002:16|No assignment to wire alu_op

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <13> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <12> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <11> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <10> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <9> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <8> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <7> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <6> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <5> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <4> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <3> of instr[17:0] is unused

@W: CL209 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":896:13:896:17|Input port bit <2> of instr[17:0] is unused

@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":893:13:893:15|Input clk is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":894:13:894:17|Input rst_n is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":904:12:904:14|Input add is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":906:12:906:14|Input mov is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":907:12:907:15|Input andr is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":908:12:908:14|Input orr is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":909:12:909:15|Input xorr is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":910:12:910:14|Input cmp is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":911:12:911:15|Input test is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":912:12:912:14|Input ror is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":913:12:913:15|Input rorc is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":914:12:914:14|Input rol is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":915:12:915:15|Input rolc is unused
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":828:10:828:23|Reference to undefined module spram16x9
@N: CG364 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":581:7:581:20|Synthesizing module isp8_flow_cntl

@N: CG179 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":715:19:715:27|Removing redundant assignment
@N: CG179 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":762:26:762:35|Removing redundant assignment
@N: CG179 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":781:25:781:33|Removing redundant assignment
@N: CG179 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":794:30:794:36|Removing redundant assignment
@N: CG179 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":807:32:807:39|Removing redundant assignment
@N: CG179 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":822:22:822:33|Removing redundant assignment
@N: CG179 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":823:22:823:32|Removing redundant assignment
@W: CG141 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":828:10:828:23|Creating black_box for spram16x9
	Making port Address an input
	Making port Data an input
Making port Clock a bidir
	Making port WE an input
	Making port ClockEn an input
Making port Q a bidir
@W: CG133 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":664:23:664:31|No assignment to din_stack
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":556:13:556:25|Reference to undefined module spram32x8
@N: CG364 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":437:7:437:18|Synthesizing module isp8_io_cntl

@W: CG141 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":556:13:556:25|Creating black_box for spram32x8
Making port Address a bidir
Making port Data a bidir
Making port Clock a bidir
	Making port WE an input
	Making port ClockEn an input
Making port Q a bidir
@E: CL175 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":513:22:513:33|Multiple non-tristate drivers for net int_mem_addr[4:0] in isp8_io_cntl
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":483:22:483:25|Input lspi is unused
@W: CL159 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":487:22:487:28|Input addr_rd is unused
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":277:5:277:16|Reference to undefined module prom
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":298:13:298:25|Reference to undefined module dpram32x8
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":311:4:311:11|Reference to undefined module GSR
@E: CG106 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":312:4:312:11|Reference to undefined module PUR
@N: CG364 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":32:7:32:10|Synthesizing module isp8

@W: CG141 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":277:5:277:16|Creating black_box for prom
Making port Address a bidir
Making port OutClock a bidir
	Making port OutClockEn an input
	Making port Reset an input
Making port Q a bidir
@W: CG141 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":298:13:298:25|Creating black_box for dpram32x8
Making port WrAddress a bidir
	Making port Data an input
Making port WrClock a bidir
Making port WE a bidir
	Making port WrClockEn an input
Making port RdAddress a bidir
Making port QR a bidir
Making port QW a bidir
@W: CG141 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":311:4:311:11|Creating black_box for GSR
Making port GSR a bidir
@W: CG141 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":312:4:312:11|Creating black_box for PUR
	Making port PUR an input
@W:"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":92:23:92:30|No assignment to wire mem_data

@W:"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":93:23:93:33|No assignment to wire int_mem_enb

@W:"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":94:23:94:29|No assignment to wire din_rd1

@W: CL168 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":312:4:312:11|Pruning instance PUR_INST - not in use ...

@E: CL175 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":91:23:91:29|Multiple non-tristate drivers for net wren_rd in isp8
@E: CL175 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":82:23:82:29|Multiple non-tristate drivers for net addr_rf[4:0] in isp8
@N: CG364 :"C:\Anto_2005\Reference_Design\isp8\anto\source\top\isp8_top_test_system.v":1:7:1:26|Synthesizing module isp8_top_test_system

@W: CG141 :"C:\Anto_2005\Reference_Design\isp8\anto\source\top\isp8_top_test_system.v":39:13:39:15|Creating black_box for orcastra_inf
Making port tst_sys_clk a bidir
Making port reset_n a bidir
Making port tst_addr a bidir
Making port tst_datain a bidir
Making port tst_sel a bidir
Making port dut_sys_clk a bidir
Making port tst_wr a bidir
Making port tst_dataout a bidir
Making port tst_ready a bidir
Making port pc_reset_out a bidir
Making port pc_datain a bidir
Making port pc_ready a bidir
Making port pc_clk a bidir
Making port pc_reset a bidir
Making port pc_dataout a bidir
Making port pc_ack a bidir
Making port pc_retry a bidir
Making port pc_err a bidir
@W: CS149 :"C:\Anto_2005\Reference_Design\isp8\anto\source\top\isp8_top_test_system.v":89:12:89:20|Port width mismatch for port speed_out.  Formal has width 2, Actual 1
@W:"C:\Anto_2005\Reference_Design\isp8\anto\source\top\isp8_top_test_system.v":69:6:69:17|No assignment to wire rst_test_reg

@W: CL157 :"C:\Anto_2005\Reference_Design\isp8\anto\source\top\isp8_top_test_system.v":34:8:34:15|*Output magma_on has undriven bits - a simulation mismatch is possible 
@W: CL157 :"C:\Anto_2005\Reference_Design\isp8\anto\source\top\isp8_top_test_system.v":35:8:35:17|*Output magma_on_r has undriven bits - a simulation mismatch is possible 
@E: CL147 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":513:22:513:33|Unresolved tristate drivers for net int_mem_addr[4:0] in isp8_io_cntl
@E: CL147 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":82:23:82:29|Unresolved tristate drivers for net addr_rf[4:0] in isp8
@E: CL147 :"C:\Anto_2005\Reference_Design\isp8\source\isp8.v":91:23:91:29|Unresolved tristate drivers for net wren_rd in isp8