isp8.srs

简单的8位CPU

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.0.0, Build 286R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Tue Jun 28 17:26:40 2005
#
#
#OPTIONS:"|-fixsmult|-IC:\\Anto_2005\\Reference_Design\\isp8\\source\\config1\\|-IC:\\Anto_2005\\Reference_Design\\isp8\\anto\\synthesis\\top\\|-IC:\\ispTOOLS5_0\\synpbase\\lib|-v2001|-autosm|-fid2|-sharing|on|-encrypt|-ui|-ram"
#CUR:"C:\\ispTOOLS5_0\\synpbase\\bin\\c_ver.exe":1105668864
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\source\\test_register\\test_register.v":1120004019
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\source\\test_register\\test_register.v":1120004019
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\source\\top\\isp8_top_test_system.v":1120004654
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\anto\\source\\top\\isp8_top_test_system.v":1120004654
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\source\\isp8.v":1118078950
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\source\\isp8.v":1118078950
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\source\\config1\\isp8_cfg.v":1118180663
#CUR:"C:\\Anto_2005\\Reference_Design\\isp8\\source\\config1\\isp8_cfg.v":1118180663
f "C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v"; # file 0
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\anto\source\top\isp8_top_test_system.v"; # file 1
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\source\isp8.v"; # file 2
af .is_verilog 1;
f "C:\Anto_2005\Reference_Design\isp8\source\config1\isp8_cfg.v"; # file 3
af .is_verilog 1;
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C;