isp8_top_test_system.srr

简单的8位CPU

@W: CS141 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x9.v":64:16:64:24|Unrecognized synthesis directive attribute
@W: CS141 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x9.v":65:16:65:24|Unrecognized synthesis directive attribute
@W: CS141 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x9.v":66:16:66:24|Unrecognized synthesis directive attribute
@W: CS141 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x9.v":67:16:67:24|Unrecognized synthesis directive attribute
@W: CS141 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x9.v":68:16:68:18|Unrecognized synthesis directive end
@I::"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v"
@N: CG334 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":18:16:18:28|Read directive translate_off 
@N: CG333 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":20:16:20:27|Read directive translate_on 
@N: CG334 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":26:16:26:28|Read directive translate_off 
@N: CG333 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":28:16:28:27|Read directive translate_on 
@N: CG334 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":34:16:34:28|Read directive translate_off 
@N: CG333 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":36:16:36:27|Read directive translate_on 
@N: CG334 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":42:16:42:28|Read directive translate_off 
@N: CG333 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":44:16:44:27|Read directive translate_on 
@N: CG334 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":50:16:50:28|Read directive translate_off 
@N: CG333 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":52:16:52:27|Read directive translate_on 
@W: CS141 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":60:16:60:20|Unrecognized synthesis directive begin
@W: CS141 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":61:16:61:24|Unrecognized synthesis directive attribute
@W: CS141 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":62:16:62:24|Unrecognized synthesis directive attribute
@W: CS141 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":63:16:63:24|Unrecognized synthesis directive attribute
@W: CS141 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":64:16:64:24|Unrecognized synthesis directive attribute
@W: CS141 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":65:16:65:24|Unrecognized synthesis directive attribute
@W: CS141 :"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\spram16x10.v":66:16:66:18|Unrecognized synthesis directive end
@I::"C:\Anto_2005\Reference_Design\isp8\models\xp\syn\xp.v"
@I::"C:\Anto_2005\Reference_Design\isp8\anto\source\test_register\test_register.v"
@I::"C:\Anto_2005\Reference_Design\isp8\anto\source\orcastra_inf\orcastra_inf.v"
Verilog syntax check successful!
File C:\Anto_2005\Reference_Design\isp8\anto\test\prom_init.v changed - recompiling
Selecting top level module orcastra_inf
@N: CG364 :"C:\Anto_2005\Reference_Design\isp8\anto\source\orcastra_inf\orcastra_inf.v":35:7:35:18|Synthesizing module orcastra_inf

@N: CL201 :"C:\Anto_2005\Reference_Design\isp8\anto\source\orcastra_inf\orcastra_inf.v":230:0:230:5|Trying to extract state machine for register tst_timegen
Extracted state machine for register tst_timegen
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@N: CL201 :"C:\Anto_2005\Reference_Design\isp8\anto\source\orcastra_inf\orcastra_inf.v":171:0:171:5|Trying to extract state machine for register load
Extracted state machine for register load
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@END
Process took 0h:00m:00s realtime, 0h:00m:00s cputime
###########################################################[
Synplicity Lattice ORCA FPGA Technology Mapper, Version 8.0.0, Build 469R, Built Mar 10 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Setting fanout limit to 100
Encoding state machine work.orcastra_inf(verilog)-load_h.load[2:0]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine work.orcastra_inf(verilog)-tst_timegen_h.tst_timegen[3:0]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
---------------------------------------
Resource Usage Report
Part: lfxp10c-3

Register bits: 51 of 9728 (1%)
I/O cells:       49

Details:
FD1P3AX:        11
FD1S3AX:        40
GSR:            1
IB:             15
INV:            1
OB:             34
ORCALUT4:       22
VHI:            1
VLO:            1
Found clock orcastra_inf|tst_sys_clk with period 1000.00ns 
Found clock orcastra_inf|pc_clk with period 1000.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jul 05 14:46:53 2005
#


Top view:               orcastra_inf
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 996.246

                             Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock               Frequency     Frequency     Period        Period        Slack       Type         Group              
---------------------------------------------------------------------------------------------------------------------------------
orcastra_inf|pc_clk          1.0 MHz       309.2 MHz     1000.000      3.234         996.766     inferred     Inferred_clkgroup_0
orcastra_inf|tst_sys_clk     1.0 MHz       266.4 MHz     1000.000      3.753         996.246     inferred     Inferred_clkgroup_1
=================================================================================================================================





Clock Relationships
*******************

Clocks                                              |    rise  to  rise     |    fall  to  fall     |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------
Starting                  Ending                    |  constraint  slack    |  constraint  slack    |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------
orcastra_inf|tst_sys_clk  orcastra_inf|tst_sys_clk  |  1000.000    996.247  |  No paths    -        |  No paths    -      |  No paths    -    
orcastra_inf|tst_sys_clk  orcastra_inf|pc_clk       |  No paths    -        |  No paths    -        |  Diff grp    -      |  No paths    -    
orcastra_inf|pc_clk       orcastra_inf|tst_sys_clk  |  No paths    -        |  No paths    -        |  No paths    -      |  Diff grp    -    
orcastra_inf|pc_clk       orcastra_inf|pc_clk       |  No paths    -        |  1000.000    996.766  |  No paths    -      |  No paths    -    
==============================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: orcastra_inf|pc_clk
====================================



Starting Points with Worst Slack
********************************

                Starting                                                       Arrival