📄 test_register.v
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// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2000-2005(c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised
// by a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement
// from Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: techsupport@latticesemi.com
// =============================================================================
// FILE DETAILS
// Project : isp8_demo
// File : test_register.v
// Description : Test Register to accomodate Orcastra interface and isp8.
// =============================================================================
// REVISION HISTORY
// Version : 1.0
// Mod. Date : July 21, 2005
// Changes Made : Initial Creation
// =============================================================================
`include "isp8_cfg.v"
module test_register(
tst_clk, // PMI Input clock
reset_n, // System Reset - Active Low
tst_sys_wr, // Register Write(High) / Read(Low) operation
tst_sys_addr, // Register Address
tst_datain, // Register Data for Write
tst_sel,
`ifdef DEMO
isp_carry_flag,
isp_instr,
isp_dout_alu,
isp_cout_alu,
isp_call_cmd,
isp_ret_cmd,
isp_bz_cmd,
`endif
// From the Modules
ext_addr,
ext_dout,
ext_io_wr,
ext_io_rd,
ext_intr_ack,
// speed_in,
// reg_loc_in,
// To the Modules
ext_io_din,
intr,
// test_reg3,
// OUT OF Test Register
// speed_out,
rst_tst_regs,
cpu_start,
reg_value,
tst_ready
);
`define TREG_IDLE 0
`define TREG_READ 1
// From the user
input tst_clk;
input reset_n;
input tst_sys_wr;
input[17:0] tst_sys_addr;
input[7:0] tst_datain;
input tst_sel;
`ifdef DEMO
input isp_carry_flag;
input[17:0] isp_instr;
input[7:0] isp_dout_alu;
input isp_cout_alu;
input isp_call_cmd;
input isp_ret_cmd;
input isp_bz_cmd;
`endif
input[7:0] ext_addr;
input[7:0] ext_dout;
input ext_io_rd;
input ext_io_wr;
input ext_intr_ack;
//input[1:0] speed_in;
//input[4:0] reg_loc_in;
output[7:0] ext_io_din;
output intr;
//output[1:0] speed_out;
output rst_tst_regs;
output cpu_start;
output[7:0] reg_value;
output tst_ready;
//output[7:0] test_reg3;
//output[7:0] reg_loc;
//reg[7:0] test_reg3;
reg[7:0] reg_value;
reg[7:0] ext_io_din;
reg intr;
// ========================
// Internal Signals
// ========================
// Registers for the 8-bit Processor
reg [7:0] TST_CTRL0;
reg [7:0] TST_CTRL1;
reg [255:0] STORE_REGS;
reg [7:0] INTR_REG;
reg [7:0] EXT_IO_DIN_REG;
`ifdef DEMO
reg [23:0] ISP_INSTR_REG;
reg [7:0] ALU_DOUT_REG;
reg CARRY_FLAG_REG;
reg COUT_ALU_REG;
reg CALL_CMD_REG;
reg RET_CMD_REG;
reg BZ_CMD_REG;
`endif
reg tstreg_access;
wire [5:0] tst_addr;
reg tst_rd;
reg tst_wr;
reg tst_regctl;
reg tst_ready;
reg[2:0] tst_type_reg;
wire rst_tst_regs;
wire cpu_start;
reg status_user_reg;
wire cpu_wr;
reg tst_ctrl0_addr;
reg tst_ctrl1_addr;
reg intr_addr;
reg ext_io_din_addr;
reg tst_reg0_addr;
reg tst_reg1_addr;
reg tst_reg2_addr;
reg tst_reg3_addr;
reg tst_reg4_addr;
reg tst_reg5_addr;
reg tst_reg6_addr;
reg tst_reg7_addr;
reg tst_reg8_addr;
reg tst_reg9_addr;
reg tst_reg10_addr;
reg tst_reg11_addr;
reg tst_reg12_addr;
reg tst_reg13_addr;
reg tst_reg14_addr;
reg tst_reg15_addr;
reg tst_reg16_addr;
reg tst_reg17_addr;
reg tst_reg18_addr;
reg tst_reg19_addr;
reg tst_reg20_addr;
reg tst_reg21_addr;
reg tst_reg22_addr;
reg tst_reg23_addr;
reg tst_reg24_addr;
reg tst_reg25_addr;
reg tst_reg26_addr;
reg tst_reg27_addr;
reg tst_reg28_addr;
reg tst_reg29_addr;
reg tst_reg30_addr;
reg tst_reg31_addr;
`ifdef DEMO
reg isp_instr_addr;
reg isp_carry_flag_addr;
reg isp_alu_dout_addr;
reg isp_cout_alu_addr;
reg isp_call_cmd_addr;
reg isp_ret_cmd_addr;
reg isp_bz_cmd_addr;
`endif
reg[7:0] tst_reg0;
reg[7:0] tst_reg1;
reg[7:0] tst_reg2;
reg[7:0] tst_reg3;
reg[7:0] tst_reg4;
reg[7:0] tst_reg5;
reg[7:0] tst_reg6;
reg[7:0] tst_reg7;
reg[7:0] tst_reg8;
reg[7:0] tst_reg9;
reg[7:0] tst_reg10;
reg[7:0] tst_reg11;
reg[7:0] tst_reg12;
reg[7:0] tst_reg13;
reg[7:0] tst_reg14;
reg[7:0] tst_reg15;
reg[7:0] tst_reg16;
reg[7:0] tst_reg17;
reg[7:0] tst_reg18;
reg[7:0] tst_reg19;
reg[7:0] tst_reg20;
reg[7:0] tst_reg21;
reg[7:0] tst_reg22;
reg[7:0] tst_reg23;
reg[7:0] tst_reg24;
reg[7:0] tst_reg25;
reg[7:0] tst_reg26;
reg[7:0] tst_reg27;
reg[7:0] tst_reg28;
reg[7:0] tst_reg29;
reg[7:0] tst_reg30;
reg[7:0] tst_reg31;
wire [32:0] my_base;
assign my_base = 32'h0000_0000;
assign tst_addr[5:0] = tst_sys_addr[5:0];
// Decoding Address Space
always @(posedge tst_clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
tstreg_access <= 1'b0;
end
else
begin
if ((tst_ready == 1'b0) && (tst_sel == 1'b1) && (tst_sys_addr[17:16] == my_base[17:16]) && (tst_sys_addr[15:12] == 4'h0))
tstreg_access <= 1'b1;
else
tstreg_access <= 1'b0;
end
end
// State Machine
always @(posedge tst_clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
tst_ready <= 1'b0;
tst_rd <= 1'b0;
tst_wr <= 1'b0;
tst_regctl <= `TREG_IDLE;
end
else
begin
case (tst_regctl)
`TREG_IDLE :
begin
if ((tst_ready == 1'b0) && (tst_sel == 1'b1) && (tst_sys_addr[17:16] == my_base[17:16]) && (tst_sys_addr[15:12] == 4'h0))
begin
tst_rd <= !tst_sys_wr;
tst_wr <= tst_sys_wr;
tst_regctl <= `TREG_READ;
end
else
begin
tst_rd <= 1'b0;
tst_wr <= 1'b0;
tst_ready <= 1'b0;
tst_regctl <= `TREG_IDLE;
end
end
`TREG_READ :
begin
if (status_user_reg == 1'b0)
begin
tst_ready <= 1'b1;
tst_regctl <= `TREG_IDLE;
end
else
begin
if (tst_ready == 1'b0)
begin
tst_ready <= 1'b1;
tst_regctl <= `TREG_READ;
end
else
begin
tst_ready <= 1'b1;
tst_regctl <= `TREG_IDLE;
end
end
end
default:
begin
tst_rd <= 1'b0;
tst_wr <= 1'b0;
tst_ready <= 1'b0;
tst_regctl <= `TREG_IDLE;
end
endcase
end
end
// =========================
// Reading The Test Register
// =========================
always @(posedge tst_clk or negedge reset_n)
begin
if (reset_n == 1'b0)
reg_value <= 8'd0;
else
begin
if (tst_rd)
begin
case(tst_addr)
6'b000000 : reg_value <= TST_CTRL0;
6'b000001 : reg_value <= TST_CTRL1;
6'b000010 : reg_value <= INTR_REG;
6'b000011 : reg_value <= EXT_IO_DIN_REG;
`ifdef DEMO
6'b010000 : reg_value <= {7'b0000000, ALU_DOUT_REG};
6'b010001 : reg_value <= ISP_INSTR_REG[7:0];
6'b010010 : reg_value <= ISP_INSTR_REG[15:8];
6'b010011 : reg_value <= ISP_INSTR_REG[23:16];
6'b010100 : reg_value <= {7'b0000000, CARRY_FLAG_REG};
6'b010101 : reg_value <= {7'b0000000, COUT_ALU_REG};
6'b010110 : reg_value <= {7'b0000000, CALL_CMD_REG};
6'b010111 : reg_value <= {7'b0000000, RET_CMD_REG};
6'b011000 : reg_value <= {7'b0000000, BZ_CMD_REG};
`endif
6'b100000 : reg_value <= STORE_REGS[7:0]; // reg0
6'b100001 : reg_value <= STORE_REGS[15:8]; // reg1
6'b100010 : reg_value <= STORE_REGS[23:16]; // reg2
6'b100011 : reg_value <= STORE_REGS[31:24];
6'b100100 : reg_value <= STORE_REGS[39:32];
6'b100101 : reg_value <= STORE_REGS[47:40];
6'b100110 : reg_value <= STORE_REGS[55:48]; // reg6
6'b100111 : reg_value <= STORE_REGS[63:56];
6'b101000 : reg_value <= STORE_REGS[71:64]; // reg8
6'b101001 : reg_value <= STORE_REGS[79:72];
6'b101010 : reg_value <= STORE_REGS[87:80];
6'b101011 : reg_value <= STORE_REGS[95:88];
6'b101100 : reg_value <= STORE_REGS[103:96];
6'b101101 : reg_value <= STORE_REGS[111:104];
6'b101110 : reg_value <= STORE_REGS[119:112];
6'b101111 : reg_value <= STORE_REGS[127:120]; // reg15
6'b110000 : reg_value <= STORE_REGS[135:128];
6'b110001 : reg_value <= STORE_REGS[143:136];
6'b110010 : reg_value <= STORE_REGS[151:144];
6'b110011 : reg_value <= STORE_REGS[159:152];
6'b110100 : reg_value <= STORE_REGS[167:160];
6'b110101 : reg_value <= STORE_REGS[175:168];
6'b110110 : reg_value <= STORE_REGS[183:176];
6'b110111 : reg_value <= STORE_REGS[191:184]; // reg23
6'b111000 : reg_value <= STORE_REGS[199:192];
6'b111001 : reg_value <= STORE_REGS[207:200];
6'b111010 : reg_value <= STORE_REGS[215:208];
6'b111011 : reg_value <= STORE_REGS[223:216];
6'b111100 : reg_value <= STORE_REGS[231:224];
6'b111101 : reg_value <= STORE_REGS[239:232]; // reg29
6'b111110 : reg_value <= STORE_REGS[247:240];
6'b111111 : reg_value <= STORE_REGS[255:248]; // reg31
default : reg_value <= 8'h00;
endcase
end
end
end
// =======================
// Input Address Decoding
// =======================
always @(posedge tst_clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
tst_ctrl0_addr <= 1'b0;
tst_ctrl1_addr <= 1'b0;
tst_reg0_addr <= 1'b0;
tst_reg1_addr <= 1'b0;
tst_reg2_addr <= 1'b0;
tst_reg3_addr <= 1'b0;
tst_reg4_addr <= 1'b0;
tst_reg5_addr <= 1'b0;
tst_reg6_addr <= 1'b0;
tst_reg7_addr <= 1'b0;
tst_reg8_addr <= 1'b0;
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