light_maker.v

来自「简单的8位CPU」· Verilog 代码 · 共 31 行

module light_maker(reset_n, data_in, light_on, enable);

input reset_n;
input[7:0] data_in;
input 	   enable;
output[7:0] light_on;
reg[7:0] light_on_temp;
reg[7:0] light_on;




always @(data_in or enable or reset_n)
begin
		
	if (!reset_n)
		light_on_temp = 8'h0f;
	else
	    begin
		if (enable)
			light_on_temp = data_in;		
		else
			light_on_temp = light_on_temp;
	    end
		

	light_on = ~light_on_temp;			
	
end
endmodule