orcastra_inf.v

简单的8位CPU

// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2001-2005 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                            408-826-6000 (other locations)
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
// U.S.A                                   email: [e-mail]
// =============================================================================
//                         FILE DETAILS
// Project          : Generic ORCAstra interface logic for HW validation test 
// File             : orcastra_inf.v
// Title            : orcastra.inf 
// Dependencies     : 
// Description      : PC Interface module used for any HW environment via
//		      ORCAstra Interface
//
// =============================================================================
//                        REVISION HISTORY
// Version          : 1.0
// Mod. Date        : May 25, 2004
// Changes Made     :
//
// =============================================================================

`timescale 1 ns / 1 ns

module orcastra_inf 
  (
   // global signals
   tst_sys_clk,
   dut_sys_clk,		
   reset_n,	
   // test register block
   tst_addr,	
   tst_datain,	
   tst_sel,	
   tst_wr,	
   tst_dataout,		//data from test register block
   tst_ready,	

   pc_reset_out,        // for reserving pc_reset
   // PC side	
   pc_datain,	
   pc_ready,	
   pc_clk,	
   pc_reset,	
   pc_dataout,   
   pc_ack,  	
   pc_retry,  	
   pc_err  	
  );
// ==============================================================================
// I/O port declaration
// ==============================================================================

input			tst_sys_clk; 	    // test system clock 
input			reset_n;	    // gsr
     //inputs from test logic blocks
input [7:0]             tst_dataout;        // dataout from test logic to pc    
input                   tst_ready; 	    // test logic ready signal
     //outputs to test logic blocks
output [17:0]           tst_addr;           // address applying to test logic  
output [7:0]            tst_datain;         // datain from pc to test logic     
output                  tst_sel;            // indicates test register address range hit   
output                  dut_sys_clk;	    // provide clock for DUT (optional)           
output                  tst_wr;             //    
     //inputs from pc
input     		pc_datain;          // serial data input from pc to test logic
input     		pc_ready;
input     		pc_clk;
input     		pc_reset;
     //outputs to pc
output     		pc_dataout;         // serial data output from test logic to pc
output     		pc_ack;
output     		pc_retry;
output     		pc_err;

output			pc_reset_out;	    // unused but intentinally assigned signal
					    // to reserve pc_reset pin location as an input

// ==============================================================================
// Output type declaration
// ==============================================================================

wire			dut_sys_clk;

reg             	tst_sel;                
reg             	tst_wr;    
reg     		pc_ack;


wire [17:0]     	tst_addr;             
wire [7:0] 	    	tst_datain;             
wire     		pc_dataout;
wire     		pc_retry;
wire     		pc_err;

wire			pc_reset_out;

reg [7:0]		read_data;
reg			load_en;
reg [7:0]		load_reg;
reg [25:0]		ad_reg;		   // temporary storage for orcastar 26 bits


// state name assignement
`define TG_SW		2
`define IDLE		0
`define TEST_SEL	1
`define PCACK		2
`define WAIT_RDY_OFF    3
`define S1		1
`define S2		2



reg [`TG_SW-1:0]	tst_timegen;
reg [`TG_SW-1:0]	load;

reg 				tst_addr_space;
reg 				wr_only;

// =============================================================================
// test logic decoding area defintion
// edit define values to make your own address space
// =============================================================================

//`define ADDR_RANGE 	tst_addr[9:0]
`define ADDR_RANGE 	tst_addr[17:8]
`define TARGET_SPACE	10'b00_0000_0000

always @(`ADDR_RANGE) begin 
   if (`ADDR_RANGE == `TARGET_SPACE) 
      tst_addr_space = 1'b1;
   else
      tst_addr_space = 1'b0;
end


//////////////////////////////////////////////////////////////////////////////////
// the statement below is to avoid the reoccurance of writing data on pc_dataout.
// In actual system it is not required, but only for better simulation reading
//////////////////////////////////////////////////////////////////////////////////

always @(posedge tst_sys_clk or negedge reset_n) begin
   if (reset_n == 1'b0) begin
      wr_only		<= 1'b0;
   end
   else begin
      if (tst_wr==1'b1)
	 wr_only <= 1'b1;
      else if (load_en==1'b0)
	 wr_only <= 1'b0;
   end
end	



// =============================================================================
// The following statements generate timing for PC clock domain 
// =============================================================================

always @(posedge tst_sys_clk or negedge reset_n) begin
   if (reset_n == 1'b0) begin
      load		<= `IDLE;
      load_en		<= 1'b0;
   end
   else begin
      case (load)
	 `IDLE : begin
	    if (pc_ready == 1'b1)	// pc_ready asserted?
	       load	<= `S1;
	    else
	       load	<= `IDLE;
	       load_en	<= 1'b0;
	 end
	 `S1 : begin
	    if (pc_clk == 1'b1)		
	       load	<= `S2;
	    else
	       load	<= `S1;
	       load_en	<= 1'b1;	// load_en asserted until pc_clk =1
	 end
	 `S2 : begin
	    if (pc_clk == 1'b0)
	       load	<= `IDLE;	// load_en de-asserted on pc_clk=0
	    else
	       load	<= `S2;
	       load_en	<= 1'b1;	// load_en keep asserted until pc_clk =0
	 end
      endcase
   end
end


always @(negedge pc_clk or negedge reset_n ) begin
   if (reset_n == 1'b0) begin
      ad_reg	<= 26'h0;			// clear address/data register
      load_reg	<= 8'b0;
   end 
   else begin
      ad_reg <= {ad_reg[24:0],pc_datain}; 	// serial to parallel conversion

      if ((load_en == 1'b1) &&(wr_only==1'b0)) // to avoid copy of write data
						// see note in bottom statement
	 load_reg	<= {read_data[0],read_data[1],read_data[2],read_data[3],
			    read_data[4],read_data[5],read_data[6],read_data[7]};
						// loading 8-bit data from test logic
      else
	 load_reg	<= {load_reg[6:0],1'b0};
   end
end


assign dut_sys_clk = tst_sys_clk;		//use the same clock resource


// =============================================================================
// The following statements generate timing for testlogic to pc handshaking
// =============================================================================

always @(posedge tst_sys_clk or negedge reset_n) begin
   if (reset_n == 1'b0) begin
      tst_timegen	<= `IDLE;
      tst_sel		<= 1'b0;
      tst_wr		<= 1'b0;
      pc_ack		<= 1'b0;
   end
   else begin
      case (tst_timegen)

	 `IDLE : begin
	    if (pc_ready == 1'b1)
	       tst_timegen	<= `TEST_SEL;
	    else begin
	       tst_timegen	<= `IDLE;
	    end
	    pc_ack		<= 1'b0;
	    tst_wr		<= 1'b0;
	 end

	 `TEST_SEL: begin
            tst_timegen 	<= `PCACK;
	    pc_ack		<= 1'b0; 	// intentional redundant statement
            if  (tst_addr_space) begin  	// if test logic address space is hit
	       tst_sel		<= 1'b1;
	       tst_wr		<= !pc_datain;
		   end
	    end

	 `PCACK: begin
	    if (tst_ready ==1'b1) begin
	       tst_timegen	<= `WAIT_RDY_OFF;
	       pc_ack		<= 1'b1; 	// ack after dataout/datain is available
	    end	
	    else begin
	       tst_timegen	<= `PCACK;
	       tst_sel		<= 1'b0;
	       tst_wr		<= 1'b0;
	       pc_ack		<= 1'b0; 	// intentional redundant statement
	    end
	 end
	    
	 `WAIT_RDY_OFF: begin
	    if (pc_ready == 1'b0) begin
	       tst_timegen	<= `IDLE;
	       pc_ack		<= 1'b0; 	// intentional redundant statement
	    end	
	    else begin
	       tst_timegen	<= `WAIT_RDY_OFF;
	       pc_ack		<= 1'b1; 	// intentional redundant statement
	    end
	 end

      endcase
   end
end



// =============================================================================
// address and data assignments after serial-to-parallel conversion
// =============================================================================
      
assign tst_addr   	= 	ad_reg[17:0];
assign tst_datain[7:0] 	=      {ad_reg[18],ad_reg[19],ad_reg[20],ad_reg[21],ad_reg[22],ad_reg[23],ad_reg[24],ad_reg[25]};  		//7:0


// =============================================================================
// address and data assignments after serial-to-parallel conversion
// =============================================================================

always @(posedge tst_sys_clk or negedge reset_n) begin
   if (reset_n == 1'b0) begin
      read_data		<= 1'b0;
   end
   else begin
      if (tst_ready && tst_addr_space)
      read_data		<= tst_dataout;
   end
end


// =============================================================================
// final dataout to pc
// =============================================================================


assign pc_dataout = load_reg[7];


// =============================================================================
// permanent assignements for pc interfacce
// =============================================================================

assign pc_retry 	= 1'b0;
assign pc_err   	= 1'b0;
assign pc_reset_out	= pc_reset;


endmodule