isp8_top_system.v

简单的8位CPU

// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2000-2005(c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised
// by a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement
// from Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation    TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                        408-826-6000 (other locations)
// Hillsboro, OR 97124                  web  : http://www.latticesemi.com/
// U.S.A                                email: [e-mail]
// =============================================================================
//                         FILE DETAILS
// Project          : isp8_demo
// File             : isp8_top_system.v
// Description      : This module is top level for isp8 system.    
// =============================================================================
//                        REVISION HISTORY
// Version          : 1.0
// Mod. Date        : July 21, 2005
// Changes Made     : Initial Creation
// =============================================================================



module isp8_top_system(tst_sys_clk,
			    reset_n,
			    pc_datain,
			    pc_ready,
			    pc_clk,
			    pc_reset,
			    pc_reset_out,
                	    pc_dataout,
                	    pc_ack,
			    pc_retry,
                            pc_err,
			    led_out,
			    light_on);

input 		tst_sys_clk;
input		reset_n;



input 		pc_datain;
input		pc_ready;
input 		pc_clk;
input		pc_reset;

output		pc_dataout;
output		pc_ack;
output		pc_retry;
output		pc_err;
output		pc_reset_out;
output[6:0]	led_out;
output[7:0]	light_on;


wire		tst_ready;
wire[17:0]	tst_addr;
wire[7:0]	tst_datain;
wire		tst_sel;
wire		dut_sys_clk;
wire		tst_wr;
wire[7:0] 	reg_value_out;
wire[7:0] 	ext_io_din;
wire	  	intr;
wire[7:0]	ext_addr;
wire[7:0]	ext_dout;
wire		ext_io_wr;
wire		ext_io_rd;
wire		intr_ack;

wire		rst_test_reg;
wire		cpu_start;

reg 		decoder_en_reg;
reg[7:0]	ext_dout_temp_reg;





orcastra_inf U1_orcastra_inf(
   .tst_sys_clk(tst_sys_clk),
   .reset_n(reset_n),	
   .tst_addr(tst_addr),	
   .tst_datain(tst_datain),	
   .tst_sel(tst_sel),	
   .dut_sys_clk(dut_sys_clk),		
   .tst_wr(tst_wr),	
   .tst_dataout(reg_value_out),		
   .tst_ready(tst_ready),	
   .pc_reset_out(pc_reset_out), 
   .pc_datain(pc_datain),	
   .pc_ready(pc_ready),	
   .pc_clk(pc_clk),	
   .pc_reset(pc_reset),	
   .pc_dataout(pc_dataout),  
   .pc_ack(pc_ack),  	
   .pc_retry(pc_retry),  	
   .pc_err(pc_err)	
  );  


light_maker U1_light_maker(
	.reset_n(reset_n),
	.data_in(ext_dout_temp_reg),
	.enable(1'b1),
	.light_on(light_on)
);

led_decoder U1_led_decoder(
	.reset_n(reset_n),
	.led_in(ext_dout_temp_reg),
	.enable(1'b1),
	.led_out(led_out)		
);




always @(posedge tst_sys_clk or negedge reset_n)
begin
	if (!reset_n)
	 
		ext_dout_temp_reg <= 8'd0;
	 
	else 
		if (ext_io_wr)
			ext_dout_temp_reg <= ext_dout;
		 
end


test_register U1_test_register(
	.tst_clk(tst_sys_clk),
	.reset_n(reset_n),
	.tst_sys_wr(tst_wr),
	.tst_sys_addr(tst_addr),
	.tst_datain(tst_datain),
	.tst_sel(tst_sel),
	.ext_addr(ext_addr),
	.ext_dout(ext_dout),
	.ext_io_wr(ext_io_wr),
	.ext_io_rd(ext_io_rd),
	.ext_intr_ack(intr_ack),
	.ext_io_din(ext_io_din),
	.intr(intr),
	.rst_tst_regs(rst_test_reg),
	.cpu_start(cpu_start),
	.reg_value(reg_value_out),
	.tst_ready(tst_ready)
	
);


isp8 U1_isp8 (
	.clk(tst_sys_clk),
	.rst_n(reset_n),
	.ext_io_din(ext_io_din),
	.intr(intr),
	.ext_addr(ext_addr),
	.ext_dout(ext_dout),
	.ext_io_wr(ext_io_wr),
	.ext_io_rd(ext_io_rd),
	.intr_ack(intr_ack)
);


endmodule