and3.v

来自「简单的8位CPU」· Verilog 代码 · 共 16 行

`resetall
`timescale 1 ns / 1 ps

`celldefine

module  AND3  (A, B, C, Z);
  input A, B, C ;
  output Z;

  and (Z, A, B, C);


endmodule 

`endcelldefine