dpram32x8.v

简单的8位CPU

/* Verilog netlist generated by SCUBA ispLever_v50_Production_Build (40) */
/* C:\ispTOOLS5_0\ispfpga\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch mg5g00 -type sdpram -rdata_width 8 -data_width 8 -num_rows 32 -outData UNREGISTERED  */
/* Tue May 10 15:21:21 2005 */


`timescale 1 ns / 1 ps
module dpram32x8 (WrAddress, Data, WrClock, WE, WrClockEn, RdAddress, QR, QW);
    input [4:0] WrAddress;
    input [7:0] Data;
    input WrClock;
    input WE;
    input WrClockEn;
    input [4:0] RdAddress;
    output [7:0] QR, QW;


    INV INV_waddr4 (.A(WrAddress[4]), .Z(waddr4_inv));

    AND3 AND3_1 (.A(WE), .B(WrClockEn), .C(waddr4_inv), .Z(dec_wre3));

    AND3 AND3_0 (.A(WE), .B(WrClockEn), .C(WrAddress[4]), .Z(dec_wre7));

    MUX21 mux_07 (.D0(mdL0_0_0), .D1(mdL0_1_0), .SD(RdAddress[4]), .Z(QR[7]));
    MUX21 mux_06 (.D0(mdL0_0_1), .D1(mdL0_1_1), .SD(RdAddress[4]), .Z(QR[6]));
    MUX21 mux_05 (.D0(mdL0_0_2), .D1(mdL0_1_2), .SD(RdAddress[4]), .Z(QR[5]));
    MUX21 mux_04 (.D0(mdL0_0_3), .D1(mdL0_1_3), .SD(RdAddress[4]), .Z(QR[4]));
    MUX21 mux_03 (.D0(mdL0_0_4), .D1(mdL0_1_4), .SD(RdAddress[4]), .Z(QR[3]));
    MUX21 mux_02 (.D0(mdL0_0_5), .D1(mdL0_1_5), .SD(RdAddress[4]), .Z(QR[2]));
    MUX21 mux_01 (.D0(mdL0_0_6), .D1(mdL0_1_6), .SD(RdAddress[4]), .Z(QR[1]));
    MUX21 mux_00 (.D0(mdL0_0_7), .D1(mdL0_1_7), .SD(RdAddress[4]), .Z(QR[0]));

    MUX21 mux_17 (.D0(mdL1_0_0), .D1(mdL1_1_0), .SD(WrAddress[4]), .Z(QW[7]));
    MUX21 mux_16 (.D0(mdL1_0_1), .D1(mdL1_1_1), .SD(WrAddress[4]), .Z(QW[6]));
    MUX21 mux_15 (.D0(mdL1_0_2), .D1(mdL1_1_2), .SD(WrAddress[4]), .Z(QW[5]));
    MUX21 mux_14 (.D0(mdL1_0_3), .D1(mdL1_1_3), .SD(WrAddress[4]), .Z(QW[4]));
    MUX21 mux_13 (.D0(mdL1_0_4), .D1(mdL1_1_4), .SD(WrAddress[4]), .Z(QW[3]));
    MUX21 mux_12 (.D0(mdL1_0_5), .D1(mdL1_1_5), .SD(WrAddress[4]), .Z(QW[2]));
    MUX21 mux_11 (.D0(mdL1_0_6), .D1(mdL1_1_6), .SD(WrAddress[4]), .Z(QW[1]));
    MUX21 mux_10 (.D0(mdL1_0_7), .D1(mdL1_1_7), .SD(WrAddress[4]), .Z(QW[0]));

    // synopsys translate_off
    defparam mem_0_0.initval =  64'h0000000000000000;
    // synopsys translate_on
    DPR16X2B mem_0_0 (.DI0(Data[6]), .DI1(Data[7]), .WCK(WrClock), .WRE(dec_wre3), 
        .RAD0(RdAddress[0]), .RAD1(RdAddress[1]), .RAD2(RdAddress[2]), .RAD3(RdAddress[3]), 
        .WAD0(WrAddress[0]), .WAD1(WrAddress[1]), .WAD2(WrAddress[2]), .WAD3(WrAddress[3]), 
        .WDO0(mdL1_0_1), .WDO1(mdL1_0_0), .RDO0(mdL0_0_1), .RDO1(mdL0_0_0))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_0_1.initval =  64'h0000000000000000;
    // synopsys translate_on
    DPR16X2B mem_0_1 (.DI0(Data[4]), .DI1(Data[5]), .WCK(WrClock), .WRE(dec_wre3), 
        .RAD0(RdAddress[0]), .RAD1(RdAddress[1]), .RAD2(RdAddress[2]), .RAD3(RdAddress[3]), 
        .WAD0(WrAddress[0]), .WAD1(WrAddress[1]), .WAD2(WrAddress[2]), .WAD3(WrAddress[3]), 
        .WDO0(mdL1_0_3), .WDO1(mdL1_0_2), .RDO0(mdL0_0_3), .RDO1(mdL0_0_2))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_0_2.initval =  64'h0000000000000000;
    // synopsys translate_on
    DPR16X2B mem_0_2 (.DI0(Data[2]), .DI1(Data[3]), .WCK(WrClock), .WRE(dec_wre3), 
        .RAD0(RdAddress[0]), .RAD1(RdAddress[1]), .RAD2(RdAddress[2]), .RAD3(RdAddress[3]), 
        .WAD0(WrAddress[0]), .WAD1(WrAddress[1]), .WAD2(WrAddress[2]), .WAD3(WrAddress[3]), 
        .WDO0(mdL1_0_5), .WDO1(mdL1_0_4), .RDO0(mdL0_0_5), .RDO1(mdL0_0_4))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_0_3.initval =  64'h0000000000000000;
    // synopsys translate_on
    DPR16X2B mem_0_3 (.DI0(Data[0]), .DI1(Data[1]), .WCK(WrClock), .WRE(dec_wre3), 
        .RAD0(RdAddress[0]), .RAD1(RdAddress[1]), .RAD2(RdAddress[2]), .RAD3(RdAddress[3]), 
        .WAD0(WrAddress[0]), .WAD1(WrAddress[1]), .WAD2(WrAddress[2]), .WAD3(WrAddress[3]), 
        .WDO0(mdL1_0_7), .WDO1(mdL1_0_6), .RDO0(mdL0_0_7), .RDO1(mdL0_0_6))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_1_0.initval =  64'h0000000000000000;
    // synopsys translate_on
    DPR16X2B mem_1_0 (.DI0(Data[6]), .DI1(Data[7]), .WCK(WrClock), .WRE(dec_wre7), 
        .RAD0(RdAddress[0]), .RAD1(RdAddress[1]), .RAD2(RdAddress[2]), .RAD3(RdAddress[3]), 
        .WAD0(WrAddress[0]), .WAD1(WrAddress[1]), .WAD2(WrAddress[2]), .WAD3(WrAddress[3]), 
        .WDO0(mdL1_1_1), .WDO1(mdL1_1_0), .RDO0(mdL0_1_1), .RDO1(mdL0_1_0))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_1_1.initval =  64'h0000000000000000;
    // synopsys translate_on
    DPR16X2B mem_1_1 (.DI0(Data[4]), .DI1(Data[5]), .WCK(WrClock), .WRE(dec_wre7), 
        .RAD0(RdAddress[0]), .RAD1(RdAddress[1]), .RAD2(RdAddress[2]), .RAD3(RdAddress[3]), 
        .WAD0(WrAddress[0]), .WAD1(WrAddress[1]), .WAD2(WrAddress[2]), .WAD3(WrAddress[3]), 
        .WDO0(mdL1_1_3), .WDO1(mdL1_1_2), .RDO0(mdL0_1_3), .RDO1(mdL0_1_2))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_1_2.initval =  64'h0000000000000000;
    // synopsys translate_on
    DPR16X2B mem_1_2 (.DI0(Data[2]), .DI1(Data[3]), .WCK(WrClock), .WRE(dec_wre7), 
        .RAD0(RdAddress[0]), .RAD1(RdAddress[1]), .RAD2(RdAddress[2]), .RAD3(RdAddress[3]), 
        .WAD0(WrAddress[0]), .WAD1(WrAddress[1]), .WAD2(WrAddress[2]), .WAD3(WrAddress[3]), 
        .WDO0(mdL1_1_5), .WDO1(mdL1_1_4), .RDO0(mdL0_1_5), .RDO1(mdL0_1_4))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_1_3.initval =  64'h0000000000000000;
    // synopsys translate_on
    DPR16X2B mem_1_3 (.DI0(Data[0]), .DI1(Data[1]), .WCK(WrClock), .WRE(dec_wre7), 
        .RAD0(RdAddress[0]), .RAD1(RdAddress[1]), .RAD2(RdAddress[2]), .RAD3(RdAddress[3]), 
        .WAD0(WrAddress[0]), .WAD1(WrAddress[1]), .WAD2(WrAddress[2]), .WAD3(WrAddress[3]), 
        .WDO0(mdL1_1_7), .WDO1(mdL1_1_6), .RDO0(mdL0_1_7), .RDO1(mdL0_1_6))
             /* synthesis initval="0x0000000000000000" */;



    // exemplar begin
    // exemplar attribute mem_0_0 initval 0x0000000000000000
    // exemplar attribute mem_0_1 initval 0x0000000000000000
    // exemplar attribute mem_0_2 initval 0x0000000000000000
    // exemplar attribute mem_0_3 initval 0x0000000000000000
    // exemplar attribute mem_1_0 initval 0x0000000000000000
    // exemplar attribute mem_1_1 initval 0x0000000000000000
    // exemplar attribute mem_1_2 initval 0x0000000000000000
    // exemplar attribute mem_1_3 initval 0x0000000000000000
    // exemplar end

endmodule