fadd2.v

来自「简单的8位CPU」· Verilog 代码 · 共 28 行

`resetall
`timescale 1 ns / 1 ps

`celldefine

module FADD2 (A0, A1,  B0, B1, CI, 
       COUT0, COUT1, S0, S1);
input  A0, A1, B0, B1, CI;
output COUT0, COUT1, S0, S1;


and INST10 (I3, CI, B0);
and INST11 (I4, A0, CI);
or  INST12 (COUT0, I3, I4, I5);
xor INST13 (S0, A0, B0, CI);
and INST2  (I5, B0, A0);

and INST22 (I17, B1, A1);
and INST23 (I15, COUT0, B1);
and INST24 (I16, A1, COUT0);
or  INST25 (COUT1, I15, I16, I17);
xor INST66 (S1, A1, B1, COUT0);


endmodule

`endcelldefine