📄 dp8ka.v
字号:
begin
for (i = 0; i < DATA_WIDTH_A; i = i+1)
begin
DOA_node_rbr[i] = v_MEM[(v_WADDR_A * DATA_WIDTH_A) + (v_WADDR_A / div_a) + i];
end
for (i = 0; i < 9; i = i+1)
begin
v_MEM[v_WADDR_A * data_width_a + i] = DIA_reg[i];
end
for (i = 0; i < 9; i = i+1)
begin
v_MEM[v_WADDR_A * data_width_a + i + 9] = DIA_reg[i + 9];
end
memchga <= ~memchga;
end
end
else if (DATA_WIDTH_A == 9)
begin
if (WRENA_reg == 1 && CLKA_valid == 1)
begin
for (i = 0; i < DATA_WIDTH_A; i = i+1)
begin
DOA_node_rbr[i] = v_MEM[(v_WADDR_A * DATA_WIDTH_A) + (v_WADDR_A / div_a) + i];
end
for (i = 0; i < data_width_a; i = i+1)
begin
v_MEM[(v_WADDR_A * data_width_a) + i] = DIA_reg[i];
end
memchga <= ~memchga;
end
end
else
begin
if (WRENA_reg == 1 && CLKA_valid == 1)
begin
for (i = 0; i < DATA_WIDTH_A; i = i+1)
begin
DOA_node_rbr[i] = v_MEM[(v_WADDR_A * DATA_WIDTH_A) + (v_WADDR_A / div_a) + i];
end
for (i = 0; i < data_width_a; i = i+1)
begin
v_MEM[(v_WADDR_A * data_width_a) + (v_WADDR_A / div_a) + i] = DIA_reg[i];
end
memchga <= ~memchga;
end
end
if (DATA_WIDTH_B == 18)
begin
if (WRENB_reg == 1 && CLKB_valid == 1)
begin
for (i = 0; i < DATA_WIDTH_B; i = i+1)
begin
DOB_node_rbr[i] = v_MEM[(v_WADDR_B * DATA_WIDTH_B) + (v_WADDR_B / div_b) + i];
end
for (i = 0; i < 9; i = i+1)
begin
v_MEM[v_WADDR_B * data_width_b + i] = DIB_reg[i];
end
for (i = 0; i < 9; i = i+1)
begin
v_MEM[v_WADDR_B * data_width_b + i + 9] = DIB_reg[i + 9];
end
memchgb <= ~memchgb;
end
end
else if (DATA_WIDTH_B == 9)
begin
if (WRENB_reg == 1 && CLKB_valid == 1)
begin
for (i = 0; i < DATA_WIDTH_B; i = i+1)
begin
DOB_node_rbr[i] = v_MEM[(v_WADDR_B * DATA_WIDTH_B) + (v_WADDR_B / div_b) + i];
end
for (i = 0; i < data_width_b; i = i+1)
begin
v_MEM[(v_WADDR_B * data_width_b) + i] = DIB_reg[i];
end
memchgb <= ~memchgb;
end
end
else
begin
if (WRENB_reg == 1 && CLKB_valid == 1)
begin
for (i = 0; i < DATA_WIDTH_B; i = i+1)
begin
DOB_node_rbr[i] = v_MEM[(v_WADDR_B * DATA_WIDTH_B) + (v_WADDR_B / div_b) + i];
end
for (i = 0; i < data_width_b; i = i+1)
begin
v_MEM[(v_WADDR_B * data_width_b) + (v_WADDR_B / div_b) + i] = DIB_reg[i];
end
memchgb <= ~memchgb;
end
end
end
end
// Read operation
always @(RENA_reg or RENB_reg or ADA_reg or ADB_reg or memchg0 or CLKA_valid or CLKB_valid or posedge RSTA_sig or posedge RSTB_sig)
begin
v_RADDR_A = ADA_reg;
v_RADDR_B = ADB_reg;
if (DATA_WIDTH_B == 36)
begin
if (RSTB_sig == 1'b1)
begin
if (RESETMODE == "SYNC")
begin
if (CLKB_node == 1'b1)
begin
DOA_node <= 0;
DOB_node <= 0;
end
end
else
begin
DOA_node <= 0;
DOB_node <= 0;
end
end
else if (CLKB_valid === 1'b1 && last_CLKB_valid === 1'b0)
begin
if (RENB_reg == 1)
begin
for (i = 0; i < DATA_WIDTH_B; i = i+1)
begin
DO_node_tr[i] = v_MEM[v_RADDR_B * DATA_WIDTH_B + i];
end
DOB_node <= DO_node_tr[35:18];
DOA_node <= DO_node_tr[17:0];
end
else if (RENB_reg == 0)
begin
if (WRITEMODE_B == "WRITETHROUGH")
begin
for (i = 0; i < DATA_WIDTH_B; i = i+1)
begin
DO_node_wt[i] = v_MEM[v_RADDR_B * DATA_WIDTH_B + i];
end
DOB_node <= DO_node_wt[35:18];
DOA_node <= DO_node_wt[17:0];
end
else if (WRITEMODE_B == "READBEFOREWRITE")
begin
DOB_node <= DO_node_rbr[35:18];
DOA_node <= DO_node_rbr[17:0];
end
end
end
end
else
begin
if (RSTA_sig == 1'b1)
begin
if (RESETMODE == "SYNC")
begin
if (CLKA_node == 1'b1)
begin
DOA_node <= 0;
end
end
else
begin
DOA_node <= 0;
end
end
else if (CLKA_valid === 1'b1 && last_CLKA_valid === 1'b0)
begin
if (RENA_reg == 1)
begin
for (i = 0; i < DATA_WIDTH_A; i = i+1)
begin
DOA_node[i] <= v_MEM[(v_RADDR_A * DATA_WIDTH_A) + (v_RADDR_A / div_a) + i];
end
end
else if (RENA_reg == 0)
begin
if (WRITEMODE_A == "WRITETHROUGH")
begin
for (i = 0; i < DATA_WIDTH_A; i = i+1)
begin
DOA_node[i] <= v_MEM[(v_RADDR_A * DATA_WIDTH_A) + (v_RADDR_A / div_a) + i];
end
end
else if (WRITEMODE_A == "READBEFOREWRITE")
begin
DOA_node <= DOA_node_rbr;
end
end
end
if (RSTB_sig == 1'b1)
begin
if (RESETMODE == "SYNC")
begin
if (CLKB_node == 1'b1)
begin
DOB_node <= 0;
end
end
else
begin
DOB_node <= 0;
end
end
else if (CLKB_valid === 1'b1 && last_CLKB_valid === 1'b0)
begin
if (RENB_reg == 1)
begin
for (i = 0; i < DATA_WIDTH_B; i = i+1)
begin
DOB_node[i] <= v_MEM[(v_RADDR_B * DATA_WIDTH_B) + (v_RADDR_B / div_b) + i];
end
end
else if (RENB_reg == 0)
begin
if (WRITEMODE_B == "WRITETHROUGH")
begin
for (i = 0; i < DATA_WIDTH_B; i = i+1)
begin
DOB_node[i] <= v_MEM[(v_RADDR_B * DATA_WIDTH_B) + (v_RADDR_B / div_b) + i];
end
end
else if (WRITEMODE_B == "READBEFOREWRITE")
begin
DOB_node <= DOB_node_rbr;
end
end
end
end
end
always @ (SR1 or DOB_node or DOA_node)
begin
if (SR1 == 1)
begin
assign DOA_reg = 0;
assign DOAB_reg = 0;
assign DOB_reg = 0;
end
else
begin
deassign DOA_reg;
deassign DOAB_reg;
deassign DOB_reg;
end
end
always @(posedge RSTA_sig or posedge CLKA_node)
begin
if (RSTA_sig == 1)
DOA_reg_async <= 0;
else
begin
if (CEA_node == 1)
DOA_reg_async <= DOA_node;
end
end
always @(posedge CLKA_node)
begin
if (CEA_node == 1)
begin
if (RSTA_sig == 1)
DOA_reg_sync <= 0;
else
DOA_reg_sync <= DOA_node;
end
end
always @(posedge RSTB_sig or posedge CLKB_node)
begin
if (RSTB_sig == 1)
begin
DOB_reg_async <= 0;
DOAB_reg_async <= 0;
end
else
begin
if (CEB_node == 1)
begin
DOB_reg_async <= DOB_node;
DOAB_reg_async <= DOA_node;
end
end
end
always @(posedge CLKB_node)
begin
if (CEB_node == 1)
begin
if (RSTB_sig == 1)
begin
DOB_reg_sync <= 0;
DOAB_reg_sync <= 0;
end
else
begin
DOB_reg_sync <= DOB_node;
DOAB_reg_sync <= DOA_node;
end
end
end
always @(DOA_reg_sync or DOA_reg_async or DOB_reg_sync or DOB_reg_async or DOAB_reg_sync or
DOAB_reg_async)
begin
if (RESETMODE == "ASYNC")
begin
DOB_reg <= DOB_reg_async;
DOA_reg <= DOA_reg_async;
DOAB_reg <= DOAB_reg_async;
end
else
begin
DOB_reg <= DOB_reg_sync;
DOA_reg <= DOA_reg_sync;
DOAB_reg <= DOAB_reg_sync;
end
end
always @(DOA_reg or DOB_reg or DOAB_reg or DOA_node or DOB_node)
begin
if (REGMODE_A == "OUTREG")
begin
if (DATA_WIDTH_B == 36)
DOA_out <= DOAB_reg;
else
DOA_out <= DOA_reg;
end
else
begin
DOA_out <= DOA_node;
end
if (REGMODE_B == "OUTREG")
DOB_out <= DOB_reg;
else
DOB_out <= DOB_node;
end
endmodule
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -