spram16x9.v

简单的8位CPU

/* Verilog netlist generated by SCUBA ispLever_v50_Production_Build (40) */
/* C:\ispTOOLS5_0\ispfpga\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch mg5g00 -type sspram -addr_width 4 -num_rows 16 -data_width 9 -outData UNREGISTERED  */
/* Fri May 20 18:13:30 2005 */


`timescale 1 ns / 1 ps
module spram16x9 (Address, Data, Clock, WE, ClockEn, Q);
    input [3:0] Address;
    input [8:0] Data;
    input Clock;
    input WE;
    input ClockEn;
    output [8:0] Q;


    AND2 AND2_0 (.A(WE), .B(ClockEn), .Z(dec_wre3));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    // synopsys translate_off
    defparam mem_0_0.initval =  64'h0000000000000000;
    // synopsys translate_on
    SPR16X2B mem_0_0 (.DI0(Data[8]), .DI1(scuba_vlo), .CK(Clock), .WRE(dec_wre3), 
        .AD0(Address[0]), .AD1(Address[1]), .AD2(Address[2]), .AD3(Address[3]), 
        .DO0(Q[8]), .DO1())
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_0_1.initval =  64'h0000000000000000;
    // synopsys translate_on
    SPR16X2B mem_0_1 (.DI0(Data[6]), .DI1(Data[7]), .CK(Clock), .WRE(dec_wre3), 
        .AD0(Address[0]), .AD1(Address[1]), .AD2(Address[2]), .AD3(Address[3]), 
        .DO0(Q[6]), .DO1(Q[7]))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_0_2.initval =  64'h0000000000000000;
    // synopsys translate_on
    SPR16X2B mem_0_2 (.DI0(Data[4]), .DI1(Data[5]), .CK(Clock), .WRE(dec_wre3), 
        .AD0(Address[0]), .AD1(Address[1]), .AD2(Address[2]), .AD3(Address[3]), 
        .DO0(Q[4]), .DO1(Q[5]))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_0_3.initval =  64'h0000000000000000;
    // synopsys translate_on
    SPR16X2B mem_0_3 (.DI0(Data[2]), .DI1(Data[3]), .CK(Clock), .WRE(dec_wre3), 
        .AD0(Address[0]), .AD1(Address[1]), .AD2(Address[2]), .AD3(Address[3]), 
        .DO0(Q[2]), .DO1(Q[3]))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_0_4.initval =  64'h0000000000000000;
    // synopsys translate_on
    SPR16X2B mem_0_4 (.DI0(Data[0]), .DI1(Data[1]), .CK(Clock), .WRE(dec_wre3), 
        .AD0(Address[0]), .AD1(Address[1]), .AD2(Address[2]), .AD3(Address[3]), 
        .DO0(Q[0]), .DO1(Q[1]))
             /* synthesis initval="0x0000000000000000" */;



    // exemplar begin
    // exemplar attribute mem_0_0 initval 0x0000000000000000
    // exemplar attribute mem_0_1 initval 0x0000000000000000
    // exemplar attribute mem_0_2 initval 0x0000000000000000
    // exemplar attribute mem_0_3 initval 0x0000000000000000
    // exemplar attribute mem_0_4 initval 0x0000000000000000
    // exemplar end

endmodule