prom.v

简单的8位CPU

/* Verilog netlist generated by SCUBA ispLever_v50_Production_Build (40) */
/* C:\ispTOOLS5_0\ispfpga\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5g00 -type bram -wp 00 -rp 1100 -addr_width 9 -data_width 18 -num_rows 512 -gsr DISABLED -resetmode ASYNC -memfile x.mem -memformat hex  */
/* Fri May 06 12:32:41 2005 */


`timescale 1 ns / 1 ps
module prom (Address, OutClock, OutClockEn, Reset, Q);
    input [8:0] Address;
    input OutClock;
    input OutClockEn;
    input Reset;
    output [17:0] Q;


    VHI scuba_vhi_inst (.Z(scuba_vhi));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    // synopsys translate_off
`define INIT_DEFPARAM
`include "prom_init.v"
`undef INIT_DEFPARAM   
    defparam prom_0_0_0.CSDECODE = "000";
    defparam prom_0_0_0.GSR = "DISABLED";
    defparam prom_0_0_0.WRITEMODE = "NORMAL";
    defparam prom_0_0_0.RESETMODE = "ASYNC";
    defparam prom_0_0_0.REGMODE = "NOREG";
    defparam prom_0_0_0.DATA_WIDTH = 18;
    // synopsys translate_on
    SP8KA prom_0_0_0 (.CE(OutClockEn), .CLK(OutClock), .WE(scuba_vlo), .CS0(scuba_vlo), 
        .CS1(scuba_vlo), .CS2(scuba_vlo), .RST(Reset), .DI0(scuba_vlo), 
        .DI1(scuba_vlo), .DI2(scuba_vlo), .DI3(scuba_vlo), .DI4(scuba_vlo), 
        .DI5(scuba_vlo), .DI6(scuba_vlo), .DI7(scuba_vlo), .DI8(scuba_vlo), 
        .DI9(scuba_vlo), .DI10(scuba_vlo), .DI11(scuba_vlo), .DI12(scuba_vlo), 
        .DI13(scuba_vlo), .DI14(scuba_vlo), .DI15(scuba_vlo), .DI16(scuba_vlo), 
        .DI17(scuba_vlo), .AD0(scuba_vlo), .AD1(scuba_vlo), .AD2(scuba_vlo), 
        .AD3(scuba_vlo), .AD4(Address[0]), .AD5(Address[1]), .AD6(Address[2]), 
        .AD7(Address[3]), .AD8(Address[4]), .AD9(Address[5]), .AD10(Address[6]), 
        .AD11(Address[7]), .AD12(Address[8]), .DO0(Q[0]), .DO1(Q[1]), .DO2(Q[2]), 
        .DO3(Q[3]), .DO4(Q[4]), .DO5(Q[5]), .DO6(Q[6]), .DO7(Q[7]), .DO8(Q[8]), 
        .DO9(Q[9]), .DO10(Q[10]), .DO11(Q[11]), .DO12(Q[12]), .DO13(Q[13]), 
        .DO14(Q[14]), .DO15(Q[15]), .DO16(Q[16]), .DO17(Q[17]))
   
`define INIT_SYNTHESIS
`include "prom_init.v"
`undef INIT_SYNTHESIS   
             /* synthesis CSDECODE="000" */
             /* synthesis GSR="DISABLED" */
             /* synthesis WRITEMODE="NORMAL" */
             /* synthesis RESETMODE="ASYNC" */
             /* synthesis REGMODE="NOREG" */
             /* synthesis DATA_WIDTH="18" */;



    // exemplar begin
`define INIT_EXEMPLAR
`include "prom_init.v"
`undef INIT_EXEMPLAR   
    // exemplar attribute prom_0_0_0 CSDECODE 000
    // exemplar attribute prom_0_0_0 GSR DISABLED
    // exemplar attribute prom_0_0_0 WRITEMODE NORMAL
    // exemplar attribute prom_0_0_0 RESETMODE ASYNC
    // exemplar attribute prom_0_0_0 REGMODE NOREG
    // exemplar attribute prom_0_0_0 DATA_WIDTH 18
    // exemplar end

endmodule