isp8.tcl

简单的8位CPU

# =============================================================================
#                           COPYRIGHT NOTICE
# Copyright 2000-2001 (c) Lattice Semiconductor Corporation
# ALL RIGHTS RESERVED
# This confidential and proprietary software may be used only as authorised by
# a licensing agreement from Lattice Semiconductor Corporation.
# The entire notice above must be reproduced on all authorized copies and
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# Lattice Semiconductor Corporation.
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# =============================================================================
#                         FILE DETAILS
# Project          : isp8
# File             : isp8.tcl
# Title            :
# Dependencies     : 
# Description      : tcl script to synthesis in synplicity's symplify pro.
# =============================================================================
#                        REVISION HISTORY
# Version          : 1.0
# Author(s)        : Umesh Ananthiah
# Mod. Date        : May 17, 2005
# Changes Made     : Initial Creation
# =============================================================================

set PROJPATH C:\\isp8_sb

#Create a new project
new_project $PROJPATH\\synthesis\\xp\\synplicity\\config1\\isp8.prj

# Set the options
set_option -technology LATTICE-XP
set_option -part LFXP3C
set_option -package T100C
set_option -grade -5
set_option -resource_sharing 1
set_option -symbolic_fsm_compiler 1
set_option -frequency 100.00
set_option -top_module isp8
set_option -_effort high
set_option -result_file $PROJPATH\\synthesis\\xp\\synplicity\\config1\\isp8.edf
set_option -include_path $PROJPATH\\source\\config1
set_option -include_path $PROJPATH\\tests
set_option -num_startend_points 10
set_option -num_critical_paths 10
#set_option -disable_io_insertion true
set_option -write_verilog 0

# add configuration file. 
   add_file -verilog $PROJPATH\\source\\config1\\isp8_cfg.v

# add model files. 
   add_file -verilog $PROJPATH\\models\\xp\\sim\\prom.v
   add_file -verilog $PROJPATH\\models\\xp\\sim\\dpram32x8.v
   add_file -verilog $PROJPATH\\models\\xp\\sim\\dpram16x8.v
   add_file -verilog $PROJPATH\\models\\xp\\sim\\spram32x8.v
   add_file -verilog $PROJPATH\\models\\xp\\sim\\spram16x8.v
   add_file -verilog $PROJPATH\\models\\xp\\sim\\spram16x9.v
   add_file -verilog $PROJPATH\\models\\xp\\syn\\xp.v

# Add top level files. 
   add_file -verilog $PROJPATH\\source\\isp8.v


# Compile first to just add constraint from sdc file
project -log_file $PROJPATH\\synthesis\\xp\\synplicity\\config1\\isp8.srr
project -run compile

# Read the constraints file
add_file -constraint $PROJPATH\\synthesis\\xp\\synplicity\\config1\\isp8.sdc

# Run synthesis now
project -run synthesis

# save and close project 
save_project $PROJPATH\\synthesis\\xp\\synplicity\\config1\\isp8.prj
#close_project $PROJPATH\\synthesis\\xp\\synplicity\\config1\\isp8.prj

# =============================================================================