📄 run_isp8.pl
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#!/usr/local/bin/perl
# $Id: simulation/nc_verilog/scripts/run_isp8.pl 1.3 2005/06/07 15:02:20PDT uananthi Exp $
# =============================================================================
# COPYRIGHT NOTICE
# Copyright 2000-2002 (c) Lattice Semiconductor Corporation
# ALL RIGHTS RESERVED
# This confidential and proprietary software may be used only as authorised by
# a licensing agreement from Lattice Semiconductor Corporation.
# The entire notice above must be reproduced on all authorized copies and
# copies may only be made to the extent permitted by a licensing agreement from
# Lattice Semiconductor Corporation.
#
# Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
# 5555 NE Moore Court 408-826-6000 (other locations)
# Hillsboro, OR 97124 web : http:#www.latticesemi.com/
# U.S.A email: techsupport@latticesemi.com
# =============================================================================
# FILE DETAILS
# Project : PCI Express x4
# File : run.pl
# Title : PCI Express simulation script
# Dependencies :
# Description :
# =============================================================================
# REVISION HISTORY
# Version : 1.0
# Author(s) : Gopi
# Mod. Date : Apr 2, 2004
# Changes Made : Initial Creation
# =============================================================================
# Use env varaibles
use Env;
use Cwd;
#==============================================================================
# USER VARIABLES
#==============================================================================
$os_used = "UNIX";
$root_dir = &root_dir($os_used);
$params_dir = "$root_dir/source/params";
$sim_dir = "$root_dir/simulation/nc_verilog/rtl";
$source_dir = "$root_dir/source";
$models_dir = "$root_dir/models";
$testbench = "$root_dir/testbench";
$tests_dir = "$root_dir/tests";
$utils_dir = "$root_dir/utils";
$syn_tool = "synplicity";
$ncvlog_exe = "$NCVERILOG_DIR/ncvlog";
$ncelab_exe = "$NCVERILOG_DIR/ncelab";
$ncsim_exe = "$NCVERILOG_DIR/ncsim";
$ncverilog_exe = "ip_ncverilog";
$run_type = "_";
$c_sim = "C_SIM" ;
$timescale = "-timescale \"1ns/100ps\"";
$defines = "+define+DEBUG=0";
#==============================================================================
# Usage
#==============================================================================
sub usage {
print "\n";
print "Usage: \n";
print "run_isp8.pl : To get Help\n";
print "run_isp8.pl -h : To get Help\n";
print "run_isp8.pl <test_case> : To run test_case with SignalScan dump \n";
print "run_isp8.pl <test_case> <DEBUG> : To get additional messages \n";
print "run_isp8.pl <test_case> <REGRESS> : For no signalscan dump \n";
print "run_isp8.pl <test_case> <NO_C_SIM> : Required for test case tc_06 \n";
print "\n";
}
$arg_num = @ARGV;
# assign the arguments to the list
@arg_list = @ARGV [0..($arg_num)];
if ($arg_num == 0) {
usage;
exit;
}
while (<@arg_list>) {
if (/NO_C_SIM/) {
$c_sim = "NO_C_SIM" ;
}
if (/DEBUG/) {
$run_type = "DEBUG" ;
$defines = "+define+DEBUG=1";
}
if (/REGRESS/) {
$run_type = "REGRESS" ;
$sim_dir = "$sim_dir/regress";
$defines = "+define+DEBUG=0 +define+REGRESS";
}
if (/SDF/) {
$run_type = "SDF" ;
$sim_dir = "$root_dir/simulation/nc_verilog/timing/synplicity";
$defines = "+define+SDF_ANNOTATE +define+DEBUG=1";
}
}
$testcase = $ARGV[0];
#==============================================================================
#==============================================================================
# Define the Test bench file
#==============================================================================
@SOURCE_FILES = (
"$source_dir/isp8.v"
);
@MODEL_FILES = (
"$models_dir/xp/sim/VHI.v",
"$models_dir/xp/sim/VLO.v",
"$models_dir/xp/sim/PUR.v",
"$models_dir/xp/sim/GSR.v",
"$models_dir/xp/sim/DP8KA.v",
"$models_dir/xp/sim/SP8KA.v",
"$models_dir/xp/sim/INV.v",
"$models_dir/xp/sim/AND2.v",
"$models_dir/xp/sim/AND3.v",
"$models_dir/xp/sim/MUX21.v",
"$models_dir/xp/sim/FADSU2.v",
"$models_dir/xp/sim/DPR16X2B.v",
"$models_dir/xp/sim/SPR16X2B.v",
"$models_dir/xp/sim/dpram32x8.v",
"$models_dir/xp/sim/dpram16x8.v",
"$models_dir/xp/sim/spram16x9.v",
"$models_dir/xp/sim/spram32x8.v",
"$models_dir/xp/sim/spram16x8.v",
"$models_dir/xp/sim/prom.v"
);
@TB_FILES = (
"$testbench/isp8_tb.v"
);
@INC_DIR = (
"+incdir+$source_dir/config3",
);
$run_dir = "$sim_dir/$testcase";
if (-d "$run_dir") {
system "/bin/rm -rf $run_dir/INCA_libs";
}
else {
mkdir ("$run_dir", 0777);
}
chdir ("$run_dir");
#print " **** $run_dir\n" ;
#==============================================================================
# Apply commands
#==============================================================================
# Generate pron init file
system "$utils_dir/isp8asm -ve -o $run_dir/prom_init.v $tests_dir/$testcase.s";
system "$utils_dir/isp8asm -vx -o $run_dir/prom_init.hex $tests_dir/$testcase.s";
if ($c_sim eq "NO_C_SIM") {
} else {
system "$utils_dir/isp8sim $run_dir/prom_init.hex > isp8sim_out.txt";
}
# Form the Verilog run Command with all arguments
$run = "$ncverilog_exe $defines @INC_DIR @TB_FILES @SOURCE_FILES @MODEL_FILES +libext+.v";
system "cp $tests_dir/$testcase.v $run_dir/testcase.v; $run";
system "/bin/rm -rf $run_dir/INCA_libs";
system "/bin/rm -rf $run_dir/testcase.v";
system "/bin/rm -rf $run_dir/prom_init.v";
system "/bin/rm -rf $run_dir/prom_init.hex";
system "/bin/rm -rf $run_dir/isp8sim_out.txt";
system "/bin/rm -rf $run_dir/lic.log";
# =============================================================================
# Define Sub Routines
# =============================================================================
sub root_dir
{
my ($os) = @_;
my $pwd = "";
if ($os eq "WINDOWS") { $pwd = getcwd;}
else { $pwd = $ENV{PWD};}
$pwd =~ s/\/\w+$//;
$pwd =~ s/\/\w+$//;
$pwd =~ s/\/\w+$//;
return $pwd;
}
sub add_dir
{
my ($dir, $val, $arr_files) = @_;
my $file;
my $i=0;
foreach $file (@$arr_files) {
@$arr_files[$i] = $val . $dir . $file;
$i++;
}
}
exit ;
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