comp5.txt

来自「实现8通道模拟/数字转换和数字/模拟转换的例子,采用ISA总线控制逻辑」· 文本 代码 · 共 32 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity COMP5 is
port (
      nG:in std_logic;
      EQ:out std_logic;
      P:in STD_LOGIC_VECTOR(6 DOWNTO 1);
      Q:in STD_LOGIC_VECTOR(6 DOWNTO 1)
		);
		
end COMP5;

architecture Behavioral of COMP5 is

BEGIN
process(NG,P)
BEGIN
IF (nG='0'and P=Q) then
    EQ<='0';
else
    EQ<='1';
end if;
end process;
end architecture Behavioral;