hc273_3.txt

来自「实现8通道模拟/数字转换和数字/模拟转换的例子,采用ISA总线控制逻辑」· 文本 代码 · 共 35 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity HC273_3 is
port(  clr,clk:in std_logic;
       D:in std_logic_vector(2 downto 0);
		 Q:out std_logic_vector(2 downto 0)
		 );
end entity HC273_3;

architecture Behavioral of HC273_3 is

begin
process(clk ,clr,D)
begin
  if (clr='0') then
     Q<="000";
  elsif (clk='1' and clk'LAST_VALUE='0' and clk'EVENT) then
	  Q<=D;
  end if;
end process;
	

end Behavioral;