hc273_8.txt

实现8通道模拟/数字转换和数字/模拟转换的例子,采用ISA总线控制逻辑

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HC273_8 is
port(  clr,clk:in std_logic;
       D:in std_logic_vector(7 downto 0);
		 Q:out std_logic_vector(7 downto 0)
		 );
end entity HC273_8;

architecture Behavioral of HC273_8 is

begin
process(clk ,clr,D)
begin
    
  if (clr='0') then
     Q<="00000000";
  elsif (clk='1' and clk'LAST_VALUE='0' and clk'EVENT) then
	  Q<=D;
  end if; 
  
end process;
	
end Behavioral;