d9bc.txt

实现8通道模拟/数字转换和数字/模拟转换的例子,采用ISA总线控制逻辑

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity D9BC is
PORT(

A,B:IN STD_LOGIC;
AB:OUT STD_LOGIC);

end D9BC;

architecture Behavioral of D9BC is

begin

 AB<='1' WHEN A='1' AND B<='1' ELSE '0';

end Behavioral;