dingceng.tan.rpt

用Verilog HDL语言编写的交通灯程序

+-------------------------------------------------------------------------------------+
; tco                                                                                 ;
+-------+--------------+------------+--------------------+---------------+------------+
; Slack ; Required tco ; Actual tco ; From               ; To            ; From Clock ;
+-------+--------------+------------+--------------------+---------------+------------+
; N/A   ; None         ; 35.000 ns  ; current_state~16   ; LAMP[7]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~14   ; LAMP[6]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~16   ; LAMP[6]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~15   ; LAMP[5]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~14   ; LAMP[5]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~16   ; LAMP[5]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~15   ; LAMP[4]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~14   ; LAMP[4]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~16   ; LAMP[4]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~14   ; LAMP[2]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~16   ; LAMP[2]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~15   ; LAMP[1]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~14   ; LAMP[1]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~16   ; LAMP[1]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~15   ; LAMP[0]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~14   ; LAMP[0]       ; CLK        ;
; N/A   ; None         ; 35.000 ns  ; current_state~16   ; LAMP[0]       ; CLK        ;
; N/A   ; None         ; 26.000 ns  ; current_state~16   ; LAMP[3]       ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; count_down[7]~reg0 ; count_down[7] ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; count_down[6]~reg0 ; count_down[6] ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; count_down[5]~reg0 ; count_down[5] ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; count_down[4]~reg0 ; count_down[4] ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; count_down[3]~reg0 ; count_down[3] ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; count_down[2]~reg0 ; count_down[2] ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; count_down[1]~reg0 ; count_down[1] ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; count_down[0]~reg0 ; count_down[0] ; CLK        ;
+-------+--------------+------------+--------------------+---------------+------------+


+--------------------------------------------------------------------------------+
; th                                                                             ;
+---------------+-------------+-----------+------+--------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                 ; To Clock ;
+---------------+-------------+-----------+------+--------------------+----------+
; N/A           ; None        ; 6.000 ns  ; EN   ; temp               ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; EN   ; count_down[7]~reg0 ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; EN   ; count_down[6]~reg0 ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; EN   ; CLK1               ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; EN   ; count_down[3]~reg0 ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; EN   ; count_down[2]~reg0 ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; EN   ; count_down[0]~reg0 ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; EN   ; count_down[1]~reg0 ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; EN   ; count_down[4]~reg0 ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; EN   ; count_down[5]~reg0 ; CLK      ;
+---------------+-------------+-----------+------+--------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed May 07 14:28:16 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dingceng -c dingceng
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "CLK1" as buffer
    Info: Detected ripple clock "CLK2" as buffer
Info: Clock "CLK" has Internal fmax of 43.48 MHz between source register "current_state~15" and destination register "count_down[5]~reg0" (period= 23.0 ns)
    Info: + Longest register to register delay is 9.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC102; Fanout = 15; REG Node = 'current_state~15'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC103; Fanout = 1; COMB Node = 'count_down[5]~479'
        Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC104; Fanout = 15; REG Node = 'count_down[5]~reg0'
        Info: Total cell delay = 7.000 ns ( 77.78 % )
        Info: Total interconnect delay =